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7-18 PPC405 Core User’s Manual
implemented for the M storage attribute because the PPC405 does not provide multi-processor
support or hardware support for data coherency.
These SPRs, called storage attribute control registers, control the various storage attributes when
address translation is disabled. When address translation is enabled, these registers are ignored, and
the storage attributes supplied by the TLB entry are used (see “TLB Fields” on page 7-3).
The storage attribute control registers divide the 4GB real address space into thirty-two 128MB
regions. In a storage attribute control register, bit 0 controls the lowest addressed 128MB region, bit 1
the next higher-addressed 128MB region, and so on. EA
0:4
specify a storage control region.
For detailed information on the function of the storage attributes, see “Storage Attribute Fields” on
page 7-5.