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DCWR
Data Cache Write-through Register
Register Summary 10-19
DCWR
SPR 0x3BA
See “Real-Mode Storage Attribute Control” on page 7-17.
Figure 10-9. Data Cache Write-through Register (DCWR)
0 W0 0 Write-back
1 Write-through
0x0000 0000 –0x07FF FFFF
1 W1 0 Write-back
1 Write-through
0x0800 0000 –0x0FFF FFFF
2 W2 0 Write-back
1 Write-through
0x1000 0000 –0x17FF FFFF
3 W3 0 Write-back
1 Write-through
0x1800 0000 –0x1FFF FFFF
4 W4 0 Write-back
1 Write-through
0x2000 0000 –0x27FF FFFF
5 W5 0 Write-back
1 Write-through
0x2800 0000 –0x2FFF FFFF
6 W6 0 Write-back
1 Write-through
0x3000 0000 –0x37FF FFFF
7 W7 0 Write-back
1 Write-through
0x3800 0000 –0x3FFF FFFF
8 W8 0 Write-back
1 Write-through
0x4000 0000 –0x47FF FFFF
9 W9 0 Write-back
1 Write-through
0x4800 0000 –0x4FFF FFFF
10 W10 0 Write-back
1 Write-through
0x5000 0000 –0x57FF FFFF
11 W11 0 Write-back
1 Write-through
0x5800 0000 –0x5FFF FFFF
12 W12 0 Write-back
1 Write-through
0x6000 0000 –0x67FF FFFF
13 W13 0 Write-back
1 Write-through
0x6800 0000 –0x6FFF FFFF
14 W14 0 Write-back
1 Write-through
0x7000 0000 –0x77FF FFFF
15 W15 0 Write-back
1 Write-through
0x7800 0000 –0x7FFF FFFF
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
W0
W1
W2
W3
W6W4 W30
W31W5
W8 W10 W12 W14
W7 W9 W11 W13 W15
W16 W18 W20 W22 W24 W26 W28
W17 W19 W21 W23 W25 W27 W29