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7-14 PPC405 Core User’s Manual
If TLB_entry[TID] = 0x00, the associated memory page is accessible to all programs, regardless of
their PID. This enables multiple processes to share common code and data. The common area is still
subject to all other access protection mechanisms. Figure 7-4 illustrates the PID.
7.7.1.2 Execute Permissions
If instruction address translation is enabled, instruction fetches are subject to MMU translation and
have MMU access protection. Fetches are inherently read-only, so write protection is not needed.
Instead, using TLB_entry[EX], a memory page is marked as executable (contains instructions) or not
executable (contains only data or memory-mapped control hardware).
If an instruction is pre-fetched from a memory page for which TLB_entry[EX] = 0, the instruction is
tagged as an error. If the processor subsequently attempts to execute this instruction, an instruction
storage interrupt results. This interrupt is precise with respect to the attempted execution. If the
fetcher discards the instruction without attempting to execute it, no interrupt will result.
Zone protection can alter execution protection.
7.7.1.3 Write Permissions
If MSR[DR] = 1, data loads and stores are subject to MMU translation and are afforded MMU access
protection. The existence of a TLB entry describing a memory page implies read access; write access
is controlled by TLB_entry[WR].
If a store (including those caused by dcbz, dcbi, or dccci) is made to an EA having
TLB_entry[WR] = 0, a data storage interrupt results. This interrupt is precise.
Zone protection can alter write protection (see “Zone Protection” on page 7-14). In addition, only zone
protection can prevent read access of a page defined by a TLB entry.
7.7.1.4 Zone Protection
Each TLB entry contains a 4-bit zone select (ZSEL) field. A zone is an arbitrary identifier for grouping
TLB entries (memory pages) for purposes of protection. As many as 16 different zones may be
defined. Any zone can have any number of member pages.
Each zone is associated with a 2-bit field (Z0−Z15) in the ZPR. The values of the field define how
protection is applied to all pages that are member of that zone. Changing the value of the ZPR field
can alter the protection attributes of all pages in the zone. Without ZPR, the change would require
finding, reading, altering, and rewriting the TLB entry for each page in a zone, individually. The ZPR
provides a much faster means of altering the protection for groups of memory pages.
Figure 7-4. Process ID (PID)
0:23 Reserved
24:31 Process ID
0 23 24 31