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vi PPC405 Core User’s Manual
The CR0 Field ...................................................................................................................................... 2-12
The Time Base .......................................................................................................................................... 2-13
Machine State Register (MSR) ................................................................................................................. 2-13
Device Control Registers .......................................................................................................................... 2-15
Data Types and Alignment ............................................................................................................................ 2-16
Alignment for Storage Reference and Cache Control Instructions ........................................................... 2-16
Alignment and Endian Operation .............................................................................................................. 2-17
Summary of Instructions Causing Alignment Exceptions ......................................................................... 2-17
Byte Ordering ............................................................................................................................................... 2-17
Structure Mapping Examples .................................................................................................................... 2-18
Big Endian Mapping ............................................................................................................................. 2-19
Little Endian Mapping ........................................................................................................................... 2-19
Support for Little Endian Byte Ordering .................................................................................................... 2-19
Endian (E) Storage Attribute ..................................................................................................................... 2-19
Fetching Instructions from Little Endian Storage Regions ................................................................... 2-20
Accessing Data in Little Endian Storage Regions ................................................................................ 2-21
PowerPC Byte-Reverse Instructions .................................................................................................... 2-21
Instruction Processing ................................................................................................................................... 2-23
Branch Processing ........................................................................................................................................ 2-24
Unconditional Branch Target Addressing Options .................................................................................... 2-24
Conditional Branch Target Addressing Options ........................................................................................ 2-24
Conditional Branch Condition Register Testing ........................................................................................ 2-25
BO Field on Conditional Branches ............................................................................................................ 2-25
Branch Prediction ...................................................................................................................................... 2-26
Speculative Accesses .................................................................................................................................... 2-27
Speculative Accesses in the PPC405 ....................................................................................................... 2-27
Prefetch Distance Down an Unresolved Branch Path .......................................................................... 2-28
Prefetch of Branches to the CTR and Branches to the LR ................................................................... 2-28
Preventing Inappropriate Speculative Accesses ....................................................................................... 2-28
Fetching Past an Interrupt-Causing or Interrupt-Returning Instruction ................................................. 2-28
Fetching Past tw or twi Instructions ...................................................................................................... 2-29
Fetching Past an Unconditional Branch ............................................................................................... 2-29
Suggested Locations of Memory-Mapped Hardware ........................................................................... 2-29
Summary ................................................................................................................................................... 2-30
Privileged Mode Operation ............................................................................................................................ 2-30
MSR Bits and Exception Handling ............................................................................................................ 2-31
Privileged Instructions ............................................................................................................................... 2-31
Privileged SPRs ........................................................................................................................................ 2-32
Privileged DCRs ........................................................................................................................................ 2-32
Synchronization ............................................................................................................................................. 2-33
Context Synchronization ........................................................................................................................... 2-33
Execution Synchronization ........................................................................................................................ 2-35
Storage Synchronization ........................................................................................................................... 2-35
Instruction Set ................................................................................................................................................ 2-36
Instructions Specific to the IBM PowerPC Embedded Environment ...................................................... 2-37
Storage Reference Instructions ................................................................................................................ 2-37
Arithmetic Instructions ............................................................................................................................... 2-38
Logical Instructions ................................................................................................................................... 2-39
Compare Instructions ................................................................................................................................ 2-39
Branch Instructions ................................................................................................................................... 2-40
CR Logical Instructions ........................................................................................................................ 2-40
Rotate Instructions ............................................................................................................................... 2-40
Shift Instructions ................................................................................................................................... 2-41
Cache Management Instructions .......................................................................................................... 2-41
Interrupt Control Instructions ..................................................................................................................... 2-41
TLB Management Instructions .................................................................................................................. 2-42