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Fixed-Point Interrupts and Exceptions 5-17
For instructions that can simultaneously generate program interrupts (privileged instructions executed
in Problem State) and data storage interrupts, the program interrupt has priority.
5.9 Instruction Storage Interrupt
The instruction storage interrupt is generated when instruction translation is active and execution is
attempted for an instruction whose fetch access to the effective address is not permitted for any of the
following reasons:
• In Problem State:
– Instruction fetch from an effective address with (ZPR field) = 00.
– Instruction fetch from an effective address with the EX bit clear and (ZPR field) ≠ 11.
– Instruction fetch from an effective address contained within a Guarded region (G=1).
• In Supervisor State:
– Instruction fetch from an effective address with the EX bit clear and (ZPR field) other than 11 or
10.
– Instruction fetch from an effective address contained within a Guarded region (G=1).
SRR0 will save the address of the instruction causing the instruction storage interrupt.
ESR is set to indicate the following conditions:
• If ESR[DIZ] = 1, the excepting condition was a zone fault: the attempted execution of an instruction
address fetched in user-mode with (ZPR field) = 00.
• If ESR[DIZ] = 0, then the excepting condition was either EX = 0 or G = 1.
The interrupt is precise with respect to the attempted execution of the instruction. Program flow
vectors to EVPR[0:15] || 0x0400.
Table 5-7. Register Settings during Data Storage Interrupts
SRR0 Written with the EA of the instruction causing the data storage interrupt
SRR1 Written with the value of the MSR at the time of the interrupt
MSR AP, APE, WE, EE, PR, FP, FE0, DWE, FE1, IR, DR←0
CE, ME, DE ← unchanged
PC EVPR[0:15] || 0x0300
DEAR Written with the EA of the failed access
ESR DST ← 1 if excepting operation is a store
DIZ ← 1 if access failure caused by a zone protection fault (ZPR[Z
n
]=00in
user mode)
U0F ← 1 if access failure caused by a U0 fault (the U0 storage attribute is
set and CCR0[U0XE] = 1)
MCI ← unchanged
All other bits are cleared.