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Instruction Set 9-101
machhwsu
Multiply Accumulate High Halfword to Word Saturate Unsigned
machhwsu
Multiply Accumulate High Halfword to Word Saturate Unsigned
prod
0:31
← (RA)
0:15
x (RB)
0:15
unsigned
temp
0:32
← prod
0:31
+ (RT)
(RT)
← (temp
1:32
∨
32
temp
0
)
The high-order halfword of RA is multiplied by the high-order halfword of RB. The unsigned product is
summed with the contents of RT and the sum is stored in a 33-bit temporary register.
If a result does not overflow, the low-order 32 bits of the temporary register are stored in RT.
If a result overflows, the returned result is the nearest representable value. Thus, if a result is greater
than 2
32
– 1, the value stored in RT is 2
32
–1.
Registers Altered
•RT
• CR[CR0]
LT, GT, EQ, SO
if Rc contains 1
• XER[SO, OV] if OE contains 1
Architecture Note
This instruction is part of the Multiply-Accumulate instruction set extensions and complies with the
architectural requirements for APUs of the IBM PowerPC Embedded Environment. As such, it is not
part of the PowerPC Architecture, nor is it part of the IBM PowerPC Embedded Environment.
Programs that use this instruction may not be portable to other implementations.
machhwsu RT, RA, RB OE=0, Rc=0
machhwsu. RT, RA, RB OE=0, Rc=1
machhwsuo RT, RA, RB OE=1, Rc=0
machhwsuo. RT, RA, RB OE=1, Rc=1
4RTRARBOE76Rc
0 6 11 16 21 22 31