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Figures xv
Figures
Figure 1-1. PPC405 Block Diagram ................................................................................................................1-4
Figure 2-1. PPC405 Programming Model—Registers .................................................................................... 2-4
Figure 2-2. General Purpose Registers (R0-R31) ..........................................................................................2-5
Figure 2-3. Count Register (CTR) ...................................................................................................................2-7
Figure 2-4. Link Register (LR) .........................................................................................................................2-7
Figure 2-5. Fixed Point Exception Register (XER) ..........................................................................................2-8
Figure 2-6. Special Purpose Register General (SPRG0–SPRG7) ...............................................................2-10
Figure 2-7. Processor Version Register (PVR) ............................................................................................. 2-10
Figure 2-8. Condition Register (CR) .............................................................................................................2-11
Figure 2-9. Machine State Register (MSR) ...................................................................................................2-14
Figure 2-10. PPC405 Data Types .................................................................................................................2-16
Figure 2-11. Normal Word Load or Store (Big Endian Storage Region) .......................................................2-22
Figure 2-12. Byte-Reverse Word Load or Store (Little Endian Storage Region) ..........................................2-22
Figure 2-13. Byte-Reverse Word Load or Store (Big Endian Storage Region) .............................................2-22
Figure 2-14. Normal Word Load or Store (Little Endian Storage Region) ....................................................2-23
Figure 2-15. PPC405 Instruction Pipeline .....................................................................................................2-24
Figure 4-1. Instruction Flow ............................................................................................................................4-4
Figure 4-2. Core Configuration Register 0 (CCR0) .......................................................................................4-11
Figure 4-3. Instruction Cache Debug Data Register (ICDBDR) ....................................................................4-14
Figure 5-1. Machine State Register (MSR) .....................................................................................................5-7
Figure 5-2. Save/Restore Register 0 (SRR0) .................................................................................................5-9
Figure 5-3. Save/Restore Register 1 (SRR1) .................................................................................................5-9
Figure 5-4. Save/Restore Register 2 (SRR2) ...............................................................................................5-10
Figure 5-5. Save/Restore Register 3 (SRR3) ...............................................................................................5-10
Figure 5-6. Exception Vector Prefix Register (EVPR) ...................................................................................5-11
Figure 5-7. Exception Syndrome Register (ESR) .........................................................................................5-11
Figure 5-8. Data Exception Address Register (DEAR) .................................................................................5-13
Figure 6-1. Relationship of Timer Facilities to the Time Base ........................................................................6-1
Figure 6-2. Time Base Lower (TBL) ................................................................................................................6-2
Figure 6-3. Time Base Upper (TBU) ...............................................................................................................6-2
Figure 6-4. Programmable Interval Timer (PIT) .............................................................................................. 6-5
Figure 6-5. Watchdog Timer State Machine ..................................................................................................6-7
Figure 6-6. Timer Status Register (TSR) ........................................................................................................6-8
Figure 6-7. Timer Control Register (TCR) .......................................................................................................6-9
Figure 7-1. Effective to Real Address Translation Flow ..................................................................................7-2
Figure 7-2. TLB Entries ...................................................................................................................................7-3
Figure 7-3. ITLB/DTLB/UTLB Address Resolution .........................................................................................7-9
Figure 7-4. Process ID (PID) .........................................................................................................................7-14
Figure 7-5. Zone Protection Register (ZPR) .................................................................................................7-15
Figure 7-6. Generic Storage Attribute Control Register ................................................................................7-19
Figure 8-1. Debug Control Register 0 (DBCR0) .............................................................................................8-4
Figure 8-2. Debug Control Register 1 (DBCR1) .............................................................................................8-6