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Contents vii
Processor Management Instructions ......................................................................................................... 2-42
Extended Mnemonics ................................................................................................................................ 2-42
Chapter 3. Initialization ..........................................................................................................3-1
Processor State After Reset ............................................................................................................................ 3-1
Machine State Register Contents after Reset ............................................................................................. 3-2
Contents of Special Purpose Registers after Reset .................................................................................... 3-3
PPC405 Initial Processor Sequencing ............................................................................................................. 3-3
Initialization Requirements ............................................................................................................................... 3-4
Initialization Code Example .............................................................................................................................. 3-5
Chapter 4. Cache Operations ................................................................................................4-1
ICU and DCU Organization and Sizes ............................................................................................................. 4-2
ICU Overview ................................................................................................................................................... 4-3
ICU Operations ............................................................................................................................................ 4-4
Instruction Cachability Control ..................................................................................................................... 4-5
Instruction Cache Synonyms ....................................................................................................................... 4-5
ICU Coherency ............................................................................................................................................ 4-6
DCU Overview ................................................................................................................................................. 4-6
DCU Operations .......................................................................................................................................... 4-6
DCU Write Strategies .................................................................................................................................. 4-7
DCU Load and Store Strategies .................................................................................................................. 4-8
Data Cachability Control .............................................................................................................................. 4-8
DCU Coherency .......................................................................................................................................... 4-9
Cache Instructions ........................................................................................................................................... 4-9
ICU Instructions ........................................................................................................................................... 4-9
DCU Instructions ....................................................................................................................................... 4-10
Cache Control and Debugging Features ....................................................................................................... 4-11
CCR0 Programming Guidelines ................................................................................................................ 4-13
ICU Debugging .......................................................................................................................................... 4-14
DCU Debugging ........................................................................................................................................ 4-15
DCU Performance .......................................................................................................................................... 4-16
Pipeline Stalls ............................................................................................................................................ 4-16
Cache Operation Priorities ........................................................................................................................ 4-17
Simultaneous Cache Operations ............................................................................................................... 4-17
Sequential Cache Operations ................................................................................................................... 4-18
Chapter 5. Fixed-Point Interrupts and Exceptions ..............................................................5-1
Architectural Definitions and Behavior ............................................................................................................. 5-1
Behavior of the PPC405 Processor Core Implementation ............................................................................... 5-2
Interrupt Handling Priorities ............................................................................................................................. 5-3
Critical and Noncritical Interrupts ..................................................................................................................... 5-5
General Interrupt Handling Registers .............................................................................................................. 5-7
Machine State Register (MSR) .................................................................................................................... 5-7
Save/Restore Registers 0 and 1 (SRR0–SRR1) ......................................................................................... 5-9
Save/Restore Registers 2 and 3 (SRR2–SRR3) ......................................................................................... 5-9
Exception Vector Prefix Register (EVPR) ................................................................................................ 5-10
Exception Syndrome Register (ESR) ........................................................................................................ 5-11
Data Exception Address Register (DEAR) ................................................................................................ 5-13
Critical Input Interrupts ................................................................................................................................... 5-13
Machine Check Interrupts .............................................................................................................................. 5-14
Instruction Machine Check Handling ......................................................................................................... 5-14
Data Machine Check Handling .................................................................................................................. 5-15
Data Storage Interrupt ................................................................................................................................... 5-16
Instruction Storage Interrupt .......................................................................................................................... 5-17
External Interrupt ........................................................................................................................................... 5-18
External Interrupt Handling ........................................................................................................................ 5-18