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Cache Operations 4-9
enabling the cache. Address translation can then be enabled, if required, and the TLB or the DCCR
can then be configured for the desired cachability
.
Programming Note: If a data block corresponding to the effective address (EA) exists in the
cache, but the EA is non-cachable, loads and stores (including dcbz) to that address are
considered programming errors (the cache block should previously have been flushed). The only
instructions that can legitimately access such an EA in the data cache are the cache
management instructions dcbf, dcbi, dcbst, dcbt, dcbtst, dccci, and dcread.
4.3.5 DCU Coherency
The DCU does not provide snooping. Application programs must carefully use cache-inhibited
regions and cache control instructions to ensure proper operation of the cache in systems where
external devices can update memory.
4.4 Cache Instructions
For detailed descriptions of the instructions described in the following sections, see Chapter 9,
“Instruction Set.”
In the instruction descriptions, the term “block” is synonymous with cache line. A block is the unit of
storage operated on by all cache block instructions.
4.4.1 ICU Instructions
The following instructions control instruction cache operations:
icbi Instruction Cache Block Invalidate
Invalidates a cache block.
icbt Instruction Cache Block Touch
Initiates a block fill, enabling a program to begin a cache block fetch before the
program needs an instruction in the block.
The program can subsequently branch to the instruction address and fetch the
instruction without incurring a cache miss.
This is a privileged instruction.
iccci Instruction Cache Congruence Class Invalidate
Invalidates the instruction cache array.
This is a privileged instruction.
icread Instruction Cache Read
Reads either an instruction cache tag entry or an instruction word from an
instruction cache line, typically for debugging. Fields in CCR0 control instruction
behavior (see “Cache Control and Debugging Features” on page 4-11).
This is a privileged instruction.