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Memory Management 7-7
7.3.3.1 ITLB Accesses
The instruction unit accesses the ITLB independently of the rest of the MMU. ITLB accesses are
transparent to the executing program, except that ITLB hits contribute to higher overall instruction
throughput by allowing data address translations to occur in parallel. Therefore, when instruction
accesses hit in the ITLB, the address translation mechanisms in the UTLB are available for use by
data accesses simultaneously.
The ITLB requests a new entry from the UTLB when an ITLB miss occurs. A four-cycle latency occurs
at each ITLB miss that is also a UTLB hit; the latency is longer if it is also a UTLB miss, or if there is
contention for the UTLB from the data side. A round-robin replacement algorithm replaces existing
entries with new entries.
7.3.4 Shadow Data TLB
To enhance performance, eight data-side TLB entries are kept in a eight-entry fully-associative
shadow array. This array, called the data TLB (DTLB), helps to avoid TLB contention between
instruction accesses to the TLB and load/store operations. Replacement and invalidation of the DTLB
entries is managed by hardware. See “Shadow TLB Consistency” on page 7-7 for details.
The DTLB can be considered a level-1 data-side TLB; the UTLB serves as the level-2 data-side TLB.
The DTLB is used only during instruction execute for storing data address translations. Each DTLB
entry contains the translation information for a page. The processor uses the DTLB for address
translation of data accesses when MSR[DR] = 1.
7.3.4.1 DTLB Accesses
The execute unit accesses the DTLB independently of the rest of the MMU. DTLB accesses are
transparent to the executing program, except that DTLB hits contribute to higher overall instruction
throughput by allowing instruction address translations to occur in parallel. Therefore, when data
accesses hit in the DTLB, the address translation mechanisms in the UTLB are available for use by
instruction accesses simultaneously.
The DTLB requests a new entry from the UTLB when a DTLB miss occurs. A three-cycle latency
occurs at each DTLB miss that is also a UTLB hit; the latency is longer if it is also a UTLB miss. If
there is contention for the UTLB from the instruction side, the data side has priority. A round-robin
replacement algorithm replaces existing entries with new entries.
7.3.5 Shadow TLB Consistency
To help maintain the integrity of the shadow TLBs, the processor invalidates the ITLB and DTLB
contents when the following context-synchronizing events occur:
• isync instruction
• Processor context switch (all interrupts, rfi, rfci)
• sc instruction
If software updates a translation/protection mechanism (UTLB, PID, ZPR, or MSR) and must
synchronize these updates with the ITLB and DTLB, the
software
must perform the necessary context
synchronization.
A typical example is the manipulation of the TLB by an operating system within an interrupt handler
for a TLB miss. Upon entry to the interrupt handler, the contents of the ITLB and DTLB are invalidated