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Overview 1-3
1.2 PowerPC Architecture
The PowerPC Architecture comprises three levels of standards:
• PowerPC User Instruction Set Architecture (UISA), including the base user-level instruction set,
user-level registers, programming model, data types, and addressing modes. This is referred to as
Book I of the PowerPC Architecture.
• PowerPC Virtual Environment Architecture, describing the memory model, cache model, cache-
control instructions, address aliasing, and related issues. While accessible from the user level,
these features are intended to be accessed from within library routines provided by the system
software. This is referred to as Book II of the PowerPC Architecture.
• PowerPC Operating Environment Architecture, including the memory management model,
supervisor-level registers, and the exception model. These features are not accessible from the
user level. This is referred to as Book III of the PowerPC Architecture.
Book I and Book II define the instruction set and facilities available to the application programmer.
Book III defines features, such as system-level instructions, that are not directly accessible by user
applications. The PowerPC Architecture is described in
The PowerPC Architecture: A Specification
for a New Family of RISC Processors
.
The PowerPC Architecture provides compatibility of PowerPC Book I application code across all
PowerPC implementations to help maximize the portability of applications developed for PowerPC
processors. This is accomplished through compliance with the first level of the architectural definition,
the PowerPC UISA, which is common to all PowerPC implementations.
1.3 The PPC405 as a PowerPC Implementation
The PPC405 implements the PowerPC UISA, user-level registers, programming model, data types,
addressing modes, and 32-bit fixed-point operations. The PPC405 fully complies with the PowerPC
UISA. The UISA 64-bit operations are not implemented, nor are the floating point operations, unless a
floating point unit (FPU) is implemented. The floating point operations, which cause exceptions, can
then be emulated by software.
Most of the features of the PPC405 are compatible with the PowerPC Virtual Environment and
Operating Environment Architectures, as implemented in PowerPC processors such as the
6xx/7xx family. The PPC405 also provides a number of optimizations and extensions to these layers
of the PowerPC Architecture. The full architecture of the PPC405 is defined by the PowerPC
Embedded Environment and the PowerPC User Instruction Set Architecture.
The primary extensions of the PowerPC Architecture defined in the Embedded Environment are:
• A simplified memory management mechanism with enhancements for embedded applications
• An enhanced, dual-level interrupt structure
• An architected DCR address space for integrated peripheral control
• The addition of several instructions to support these modified and extended resources
Finally, some of the specific implementation features of the PPC405 are beyond the scope of the
PowerPC Architecture. These features are included to enhance performance, integrate functionality,
and reduce system complexity in embedded control applications.