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Overview 1-9
significant byte). See “Byte Ordering” on page 2-17 for more information about big and little endian
operation.
1.4.7 Processor Core Register Set Summary
The processor core registers can be grouped into basic categories based on function and access
mode: general purpose registers (GPRs), special purpose registers (SPRs), the machine state
register (MSR), the condition register (CR), and, in Core+ASIC implementations, device control
registers (DCRs).
Chapter 10, “Register Summary,” provides a register diagram and a register field description table for
each register.
1.4.7.1 General Purpose Registers
The processor core contains 32 GPRs; each register contains 32 bits. The contents of the GPRs can
be transferred from memory using load instructions and stored to memory using store instructions.
GPRs, which are specified as operands in many instructions, can also receive instruction results and
the contents of other registers.
1.4.7.2 Special Purpose Registers
Special Purpose Registers (SPRs), which are part of the PowerPC Architecture, are accessed using
the mtspr and mfspr instructions. SPRs control the use of the debug facilities, timers, interrupts,
storage control attributes, and other architected processor resources.
All SPRs are privileged (unavailable to user-mode programs), except the Count Register (CTR), the
Link Register (LR), SPR General Purpose Registers (SPRG4–SPRG7, read-only), and the Fixed-
point Exception Register (XER). Note that access to the Time Base Lower (TBL) and Time Base
Upper (TBU) registers, when addressed as SPRs, is write-only and privileged. However, when
addressed as Time Base Registers (TBRs), read access to these registers is not privileged. See
“Time Base Registers” on page 10-4 for more information.
1.4.7.3 Machine State Register
The PPC405 contains a 32-bit Machine State Register (MSR). The contents of a GPR can be written
to the MSR using the mtmsr instruction, and the MSR contents can be read into a GPR using the
mfmsr instruction. The MSR contains fields that control the operation of the processor core.
1.4.7.4 Condition Register
The PPC405 contains a 32-bit Condition Register (CR). These bits are grouped into eight 4-bit fields,
CR[CR0]–CR[CR7]. Instructions are provided to perform logical operations on CR fields and bits
within fields and to test CR bits within fields. The CR fields, which are set by compare instructions,
can be used to control branches. CR[CR0] can be set implicitly by arithmetic instructions.
1.4.7.5 Device Control Registers
DCRs, which are architecturally outside of the processor core, are accessed using the mtdcr and
mfdcr instructions. DCRs are used to control, configure, and hold status for various functional units
that are not part of the processor core. Although the PPC405 does not contain DCRs, the mtdcr and
mfdcr instructions are provided.