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X-10 PPC405 Core User’s Manual
from little endian storage 2-20
instruction fields A-41
instruction formats 9-2
, A-41
diagrams A-43
instruction forms A-41
, A-43
instruction queue
illustrated 2-24
role in processing instructions 2-23
instruction set
brief summaries by category 2-36
for embedded processors 2-37
instruction set portability 9-1
instruction set summary
cache control 2-41
CR logical 2-40
instruction storage interrupts
causes 5-17
register settings 5-18
instruction timings C-3
branches and cr logicals C-3
general rules C-3
instruction cache misses C-7
loads and stores C-7
strings C-6
instruction TLB.
See
ITLB
instructions
alphabetical, including extended mnemonics A-1
arithmetic and logical 2-38
, B-33
arithmetic compares 2-11
branch 2-40
, B-38
branch conditional, testing CTR 2-25
byte-reverse, usefulness of 2-21
cache
DAC debug events 8-15
cache control B-41
cache control, alignment of 2-16
compare 2-39
comparison B-39
condition register logical B-37
context synchronizing, defined 2-33
CR logical 2-39
extended mnemonics B-9
format diagrams A-43
formats A-41
forms A-41
, A-43
ICU controlling 4-9
interrupt control 2-41
, B-42
logical compares 2-11
opcodes A-33
privileged B-7
privileged, listed 2-31
processor management 2-42
, B-44
for reading DCRs 2-32
for reading privileged SPRs 2-32
rotate and shift B-40
specific to PowerPC Embedded Controllers B-5
storage reference B-29
storage reference, alignment of 2-16
storage reference, in core 2-37
TLB management 2-42
, B-42
interfaces
interrupt controller 1-8
interrupt controller interface 1-8
interrupts
alignment 2-17
register settings 5-19
summary 5-19
asynchronous, defined 5-1
behavior 5-1
critical
defined 5-5
processing 5-6
critical input 5-13
data machine check 5-15
data storage 5-16
, 7-10
register settings 5-17
debug, register settings 5-26
defined 5-1
DTLB miss 7-11
DTLB, register settings 5-25
external
programming note 5-18
register settings 5-19
fetching past, speculatively 2-28
FIT, causes 5-23
FIT, register settings 5-24
handling as critical 5-3
handling priorities 5-3
handling priorities, illustrated 5-4
imprecise, defined 5-1
instruction storage 7-10
causes 5-17
register settings 5-18
ITLB miss 7-11
ITLB miss, registers 5-25
machine check, causes of 5-14
machine check, defined 5-2
machine check—instruction
handling 5-14
register settings 5-15
synchronism 5-3
noncritical
defined 5-5
processing 5-5
PIT, register settings 5-22
precise handling 5-2
precise, defined 5-1
program 7-11
causes 5-20
ESR usage 5-20
register settings 5-21
register settings during critical 5-14
synchronous, defined 5-2
system call, register settings 5-22
TLB miss, preventing 7-11
TLB-related 7-9
vector offsets, illustrated 5-6
WDT, causes 5-24
WDT, register settings 5-24
isync 9-70
and ITLB 7-7
context synchronization, example 2-35