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9-168 PPC405 Core User’s Manual
stswx
Store String Word Indexed
However, the architecture makes no statement regarding imprecise exceptions related to stswx when
XER[TBC] = 0. IBM PowerPC processors generate an imprecise exception (machine check) on this
instruction when all of the following conditions are true:
• The instruction passes all protection bounds checking
• The address is cachable
• The address is passed to the data cache
• The address misses in the data cache (resulting in a line fill request)
• The address encounters some form of bus error (non-configured, for example)
Architecture Note
This instruction is part of the PowerPC User Instruction Set Architecture.