Filter
Top Products
Memory Management 7-11
See “Zone Protection” on page 7-14 for a detailed discussion of zone protection. See “Instruction
Storage Interrupt” on page 5-17 for a detailed discussion of the instruction storage interrupt.
7.4.3 Data TLB Miss Interrupt
A data TLB miss interrupt is generated if data address translation is enabled and a valid TLB entry
matching the EA and PID is not present. The interrupt applies to data access instructions and cache
operations (excluding cache touch instructions).
See “Data TLB Miss Interrupt” on page 5-25 for a detailed discussion.
7.4.4 Instruction TLB Miss Interrupt
The instruction TLB miss interrupt is generated if instruction address translation is enabled and
execution is attempted for an instruction for which a valid TLB entry matching the EA and PID for the
instruction fetch is not present.
See “Instruction TLB Miss Interrupt” on page 5-25 for a detailed discussion.
7.4.5 Program Interrupt
When the TIE_cpuMmuEn signal is tied to 0, the TLB instructions (tlbia, tlbre, tlbsx, tlbsync, and
tlbwe) are treated as illegal instructions. When execution of any of these instructions occurs under
this circumstance, a program interrupt results.
See “Program Interrupt” on page 5-20 for a detailed discussion.
When TIE_cpuMmuEn is tied to 0, MSR[IR,DR] = 0.
Programming Note: When TIE_cpuMmuEn is tied to 0, MSR[IR,DR] = 0 upon execution of an rfi
or rfci instruction, even if an interrupt handler sets MSR[IR] = 1 or MSR[DR] = 1 in Save/Restore
Register 0 (SRR0) or SRR3.
See “Program Interrupt” on page 5-20 for a detailed discussion.
7.5 TLB Management
The processor does not imply any format for the page tables or the page table entries because there
is no hardware support for page table management. Software has complete flexibility in implementing
a replacement strategy, because software does the replacing. For example, software can “lock” TLB
entries that correspond to frequently used storage by electing to never replace them, so that those
entries are never cast out of the TLB.
TLB management is performed by software with some hardware assist, consisting of:
• Storage of the missed EA in the Save/Restore Register 0 (SRR0) for an instruction-side miss, or in
the Data Exception Address Register (DEAR) for a data-side miss.
• Instructions for reading, writing, searching, and invalidating the TLB, as described briefly in the
following subsections. See Chapter 9, “Instruction Set,” for detailed instruction descriptions.