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xx PPC405 Core User’s Manual
Table 9-23. Extended Mnemonics for mtspr ................................................................................................ 9-120
Table 9-24. Extended Mnemonics for nor, nor. ........................................................................................... 9-139
Table 9-25. Extended Mnemonics for or, or. ............................................................................................... 9-140
Table 9-26. Extended Mnemonics for ori ..................................................................................................... 9-142
Table 9-27. Extended Mnemonics for rlwimi, rlwimi. ................................................................................... 9-146
Table 9-28. Extended Mnemonics for rlwinm, rlwinm. ................................................................................. 9-147
Table 9-29. Extended Mnemonics for rlwnm, rlwnm. .................................................................................. 9-150
Table 9-30. Extended Mnemonics for subf, subf., subfo, subfo. ................................................................. 9-176
Table 9-31. Extended Mnemonics for subfc, subfc., subfco, subfco. .......................................................... 9-177
Table 9-32. Extended Mnemonics for tlbre .................................................................................................. 9-185
Table 9-33. Extended Mnemonics for tlbwe ................................................................................................ 9-189
Table 9-34. Extended Mnemonics for tw ..................................................................................................... 9-191
Table 9-35. Extended Mnemonics for twi .................................................................................................... 9-194
Table 10-1. PPC405 General Purpose Registers........................................................................................... 10-1
Table 10-2. Special Purpose Registers ......................................................................................................... 10-2
Table 10-3. Time Base Registers................................................................................................................... 10-4
Table A-1. PPC405 Instruction Syntax Summary ........................................................................................... A-1
Table A-2. PPC405 Instructions by Opcode ................................................................................................. A-33
Table B-1. PPC405 Instruction Set Categories ............................................................................................... B-1
Table B-2. Implementation-specific Instructions ............................................................................................. B-1
Table B-3. Instructions in the IBM PowerPC Embedded Environment ........................................................... B-5
Table B-4. Privileged Instructions ................................................................................................................... B-7
Table B-5. Extended Mnemonics for PPC405 .............................................................................................. B-10
Table B-6. Storage Reference Instructions .................................................................................................. B-29
Table B-7. Arithmetic and Logical Instructions ............................................................................................. B-33
Table B-8. Condition Register Logical Instructions ....................................................................................... B-37
Table B-9. Branch Instructions ..................................................................................................................... B-38
Table B-10. Comparison Instructions ........................................................................................................... B-39
Table B-11. Rotate and Shift Instructions ..................................................................................................... B-40
Table B-12. Cache Control Instructions ........................................................................................................ B-41
Table B-13. Interrupt Control Instructions ..................................................................................................... B-42
Table B-14. TLB Management Instructions .................................................................................................. B-42
Table B-15. Processor Management Instructions ........................................................................................ B-44
Table C-1. Cache Sizes, Tag Fields, and Lines .............................................................................................. C-2
Table C-2. Multiply and MAC Instruction Timing ............................................................................................. C-5
Table C-3. Instruction Cache Miss Penalties................................................................................................... C-7