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Programming Model 2-17
Misalignments are addresses that are not naturally aligned on data type boundaries. An address not
divisible by four is misaligned with respect to word instructions. An address not divisible by two is
misaligned with respect to halfword instructions. The PPC405 core implementation handles
misalignments within and across word boundaries, but there is a performance penalty because
additional cycles are required.
2.4.2 Alignment and Endian Operation
The endian storage control attribute does not affect alignment behavior. In little endian storage
regions, the alignment of data is treated as it is in big endian storage regions; no special alignment
exceptions occur when accessing data in little endian storage regions. Note that the alignment
exceptions that apply to big endian region accesses also apply to little endian storage region
accesses.
2.4.3 Summary of Instructions Causing Alignment Exceptions
Table 2-5 summarizes the instructions that cause alignment exceptions and the conditions under
which the alignment exceptions occur.
2.5 Byte Ordering
The following discussion describes the “endianness” of the PPC405, which, by default and in normal
use is “big endian.”
If scalars (individual data items and instructions) were indivisible, “byte ordering” would not be a
concern. It is meaningless to consider the order of bits or groups of bits within a byte, the smallest
addressable unit of storage; nothing can be observed about such order. Only when scalars, which the
programmer and processor regard as indivisible quantities, can comprise more than one addressable
unit of storage does the question of byte order arise.
For a machine in which the smallest addressable unit of storage is the 32-bit word, there is no
question of the ordering of bytes within words. All transfers of individual scalars between registers and
storage are of words, and the address of the byte containing the high-order eight bits of a scalar is the
same as the address of any other byte of the scalar.
For the PowerPC Architecture, as for most computer architectures currently implemented, the
smallest addressable unit of storage is the 8-bit byte. Other scalars are halfwords, words, or
doublewords, which consist of groups of bytes. When a word-length scalar is moved from a register to
Table 2-5. Alignment Exception Summary
Instructions Causing Alignment
Exceptions Conditions
dcbz EA in non-cachable or write-through storage
dcread, lwarx, stwcx. EA not word-aligned
APU load/store halfword EA not halfword-aligned
APU load/store word EA not word-aligned
APU load/store doubleword EA not word-aligned