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2-42 PPC405 Core User’s Manual
2.11.8 TLB Management Instructions
The TLB management instructions read and write entries of the TLB array in the MMU, search the
TLB array for an entry which will translate a given address, and invalidate all TLB entries. There is
also an instruction for synchronizing TLB updates with other processors, but because the PPC405
core is for use in uniprocessor environments, this instruction performs no operation.
Table 2-23 lists the TLB management instructions. In the table, the syntax “[.]” indicates that the
instruction has a “record” form that updates CR[CR0], and a “non-record” form.
2.11.9 Processor Management Instructions
These instructions move data between the GPRs and SPRs, the CR, and DCRs in the PPC405 core,
and provide traps, system calls, and synchronization controls.
Table 2-24 lists the processor management instructions in the PPC405 core.
2.11.10 Extended Mnemonics
In addition to mnemonics for instructions supported directly by hardware, the PowerPC Architecture
defines numerous
extended mnemonics
.
An extended mnemonic translates directly into the mnemonic of a hardware instruction, typically with
carefully specified operands. For example, the PowerPC Architecture does not define a “shift right
word immediate” instruction, because the “rotate left word immediate then AND with mask,” (rlwinm)
instruction can accomplish the same result:
rlwinm RA,RS,32–n,n,31
However, because the required operands are not obvious, the PowerPC Architecture defines an
extended mnemonic:
srwi RA,RS,n
Extended mnemonics transfer the problem of remembering complex or frequently used operand
combinations to the assembler, and can more clearly reflect a programmer’s intentions. Thus,
programs can be more readable.
Table 2-23. TLB Management Instructions
tlbia
tlbre
tlbsx[.]
tlbsync
tlbwe
Table 2-24. Processor Management Instructions
eieio
isync
sync
mcrxr
mfcr
mfdcr
mfspr
mtcrf
mtdcr
mtspr
sc
tw
twi