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1-6 PPC405 Core User’s Manual
associative; a page entry can be placed anywhere in the TLB. The translation function of the MMU
occurs pre-cache for data accesses. Cache tags and indexing use physical addresses for data
accesses; instruction fetches are virtually indexed and physically tagged.
Software manages the establishment and replacement of TLB entries. This gives system software
significant flexibility in implementing a custom page replacement strategy. For example, to reduce
TLB thrashing or translation delays, software can reserve several TLB entries for globally accessible
static mappings. The instruction set provides several instructions to manage TLB entries. These
instructions are privileged and require the software to be executing in supervisor state. Additional TLB
instructions are provided to move TLB entry fields to and from GPRs.
The MMU divides logical storage into pages. Eight page sizes (1KB, 4KB, 16KB, 64KB, 256KB, 1MB,
4MB, 16MB) are simultaneously supported, so that, at any given time, the TLB can contain entries for
any combination of page sizes. For a logical to physical translation to occur, a valid entry for the page
containing the logical address must be in the TLB. Addresses for which no TLB entry exists cause
TLB-Miss exceptions.
To improve performance, 4 instruction-side and 8 data-side TLB entries are kept in shadow arrays.
The shadow arrays prevent TLB contention. Hardware manages the replacement and invalidation of
shadow-TLB entries; no system software action is required. The shadow arrays can be thought of as
level 1 TLBs, with the main TLB serving as a level 2 TLB.
When address translation is enabled, the translation mechanism provides a basic level of protection.
Physical addresses not mapped by a page entry are inaccessible when translation is enabled. Read
access is implied by the existence of the valid entry in the TLB. The EX and WR bits in the TLB entry
further define levels of access for the page, by permitting execute and write access, respectively.
The Zone Protection Register (ZPR) enables the system software to override the TLB access
controls. For example, the ZPR provides a way to deny read access to application programs. The
ZPR can be used to classify storage by type; access by type can be changed without manipulating
individual TLB entries.
The PowerPC Architecture provides WIU0GE (write-back/write through, cachability, user-defined 0,
guarded, endian) storage attributes that control memory accesses, using bits in the TLB or, when
address translation is disabled, storage attribute control registers.
When address translation is enabled (MSR[IR, DR] = 1), storage attribute control bits in the TLB
control the storage attributes associated with the current page. When address translation is disabled
(MSR[IR, DR] = 0), bits in each storage attribute control register control the storage attributes
associated with storage regions. Each storage attribute control register contains 32 fields. Each field
sets the associated storage attribute for a 128MB memory region. See “Real-Mode Storage Attribute
Control” on page 7-17 for more information about the storage attribute control registers.
1.4.3 Timer Facilities
The processor core contains a time base and three timers:
• Programmable Interval Timer (PIT)
• Fixed Interval Timer (FIT)
• Watchdog timer