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ITLB (instruction translation lookaside buffer)
accesses 7-7
consistency 7-7
defined 7-6
miss interrupts 5-25
, 7-11
programming note 7-8
L
lbz 9-71
lbzu 9-72
lbzx 9-74
lha 9-75
lhau 9-76
lhax 9-78
lhbrx 9-79
lhz 9-80
lhzu 9-81
lhzux 9-82
lhzx 9-83
li 9-9
Link Register.
See
LR
lis 9-12
little endian
alignment 2-17
byte ordering supported 2-19
defined 2-18
mapping 2-19
storage attributes 2-20
storage regions
accessing data from 2-21
byte-reverse instructions 2-21
- 2-23
fetching instructions from 2-20
lmw 9-84
load strategies, controlled by DCU 4-8
logical compares 2-11
logical instructions
CR 2-39
overview 2-38
LR 10-31
LR (Link Register)
branch instructions 2-40
function 2-7
lswi 9-85
lswx 9-87
lwarx 9-89
lwz 9-91
lwzu 9-92
lwzux 9-93
lwzx 9-94
M
macchw 9-95
macchws 9-96
macchwsu 9-97
macchwu 9-98
machhw 9-99
machhwsu 9-101
machhwu 9-102
machine check interrupts
causes 5-14
defined 5-2
machine check—instruction interrupts
handling 5-14
register settings 5-15
synchronism 5-3
Machine State Register.
See
MSR
maclhw 9-103
maclhws 9-104
, 9-138
maclhwu 9-106
mapping
big endian 2-19
little endian 2-19
structure, examples 2-18
mcrf 9-107
mcrxr 9-108
memory mapping
of hardware 2-29
memory models, non-supported 4-8
, 7-5
memory organization 2-1
mfcr 9-109
mfdcr 9-110
mfmsr 9-111
mfspr 9-112
mftb 9-115
mftbu 9-115
misalignments, defined 2-17
MMU (memory management unit)
accesses, interrupts from 7-10
, 7-11
address translation 7-1
data storage interrupts 7-10
DTLB miss interrupts 7-11
execute permissions 7-14
general access protection 7-13
instruction storage interrupts 7-10
ITLB miss interrupts 7-11
MSR and access protection 7-13
overview 1-5
program interrupts 7-11
recording page references and changes 7-12
TLB management 7-11
zone protection 7-14
mnemonics,extended.
See
extended mnemonics
modes
execution 2-31
real, storage attribute control 7-17
mr 9-140
mr. 9-140
MSR 2-13
, 10-32
MSR (Machine State Register)
bits and exception handling 2-31
contents after resets 3-2
controlling execution mode 2-31
DR bit 7-1
illustrated 5-7
interrupt control instructions 2-41
IR bit 7-1
programming note 5-7
summarized 1-9
mtcr 9-116
mtcrf 9-116
mtdcr 9-117
mtmsr
execution synchronization 2-35