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X-4 PPC405 Core User’s Manual
data TLB.
See
DTLB
data types
illustrated 2-16
summarized 1-8
DBCR 8-4
DBCR0 10-11
, 10-13
DBCR0 (Debug Control Register 0)
resets 3-1
DBSR 8-7
, 10-15
dcba
does not cause interrupts 7-16
functions 4-10
dcbf 9-49
data storage interrupts 7-17
functions 4-10
dcbi 9-50
data storage interrupts 7-16
functions 4-10
dcbst 9-51
data storage interrupts 7-17
functions 4-10
dcbt 9-52
data storage interrupts 7-17
functions 4-10
dcbtst
functions 4-10
dcbz 9-54
data storage interrupts 7-16
functions 4-11
dccci 9-56
data storage interrupts 7-16
functions 4-11
when use not recommended 7-17
DCCR 10-17
DCCR (Data Cache Cachability Register)
controlling cachability 4-8
controlling the caching inhibited (I) storage attribute
7-20
dcread 9-57
controlled by CCR0 4-11
as debugging tool 4-15
functions 4-11
DCRs (device control registers)
instructions for reading 2-32
summary 1-9
uses for 2-15
DCU (data cache unit)
cachability control 4-8
cache line fills 4-6
coherency 4-9
debugging 4-15
features 4-1
instructions 4-10
load commands, accepting 4-17
load strategies 4-8
overview 4-6
performance 4-16
pipeline stalls 4-16
priority changes 4-17
priority signal 4-17
sequential caching 4-18
simultaneous cache operations 4-17
store commands 4-17
tag information in GPRs 4-16
write strategies 4-7
DCWR 10-19
DCWR (Data Cache Write-through Register)
controlling write strategies 4-7
write-through policy 7-19
DEAR 10-21
DEAR (Data Exception Address Register)
illustrated 5-13
Debug Control Register (DBCR) 8-4
Debug Control Register 0.
See
DBCR0
debug interrupts
register settings 5-26
debugging
boundary scan chain 8-21
DCU 4-15
debug events 8-10
debug interfaces 8-19
JTAG test access port 8-19
trace status port 8-22
development tools 8-1
ICU 4-14
modes 8-1
external 8-2
internal 8-1
real-time trace 8-3
processor control 8-3
processor status 8-4
Device Control Registers.
See
DCRs
dirty cache line, defined 4-16
divw 9-59
divw. 9-59
divwo 9-59
divwo. 9-59
divwu 9-60
divwu. 9-60
divwuo 9-60
divwuo. 9-60
DTLB (data translation lookaside buffer)
accesses 7-7
miss interrupts 5-25
, 7-11
summary 7-7
E
EA (effective address)
forming 2-16
translation to RA, illustrated 7-2
when non-cachable 4-9
EAs (effective addresses)
indexing the cache array 4-5
effective address.
See
EA
effective addresses.
See
EAs
eieio 9-61
storage synchronization 2-36
embedded processors
instruction set 2-37
endian (E) storage attribute
and byte-reverse load/store instructions 2-23
controlled by SLER 7-20
and little endian 2-19