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Programming Model 2-33
2.10 Synchronization
The PPC405 core supports the synchronization operations of the PowerPC Architecture. The
following book, chapter, and section numbers refer to related information in
The PowerPC
Architecture: A Specification for a New Family of RISC Processors
:
• Book II, Section 1.8.1, “Storage Access Ordering” and “Enforce In-order Execution of I/O”
• Book III, Section 1.7, “Synchronization”
• Book III, Chapter 7, “Synchronization Requirements for Special Registers and Lookaside Buffers”
2.10.1 Context Synchronization
The context of a program is the environment (for example, privilege and address translation) in which
the program executes. Context is controlled by the content of certain registers, such as the Machine
State Register (MSR), and includes the content of all GPRs and SPRs.
An instruction or event is context synchronizing if it satisfies the following requirements:
1. All instructions that
precede
a context synchronizing operation must complete in the context that
existed
before
the context synchronizing operation.
2. All instructions that
follow
a context synchronizing operation must complete in the context that
exists
after
the context synchronizing operation.
Such instructions and events are called “context synchronizing operations.” In the PPC405 core,
these include any interrupt, except a non-recoverable instruction machine check, and the isync, rfci,
rfi, and sc instructions.
However, context specifically excludes the contents of memory. A context synchronizing operation
does not guarantee that subsequent instructions observe the memory context established by
previous instructions. To guarantee memory access ordering in the PPC405 core, one must use
either an eieio instruction or a sync instruction. Note that for the PPC405 core, the eieio and sync
instructions are implemented identically. See “Storage Synchronization” on page 2-35.
The contents of DCRs are not considered as part of the processor “context” managed by a context
synchronizing operation. DCRs are not part of the processor core, and are analogous to memory-
mapped registers. Their context is managed in a manner similar to that of memory contents.
Finally, implementations of the PowerPC Architecture can exempt the machine check exception from
context synchronization control. If the machine check exception is exempted, an instruction that
precedes
a context synchronizing operation can cause a machine check exception
after
the context
synchronizing operation occurs and additional instructions have completed.
The following scenarios use pseudocode examples to illustrate these limitations of context
synchronization. Subsequent text explains how software can further guarantee “storage ordering.”
1. Consider the following instruction sequence:
STORE non-cachable to address XYZ
isync
XYZ instruction