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Programming Model 2-35
isync guarantees that all subsequent instructions are fetched and executed using the context
established by all previous instructions. isync is a context synchronizing operation; isync causes all
subsequently prefetched instructions to be discarded and refetched.
The following example illustrates the use of isync with debug exceptions:
mtdbcr0 Enable an instruction address compare (IAC) event
isync Wait for the new Debug Control Register 0 (DBCR0) context to be established
XYZ This instruction is at the IAC address; an isync was necessary to guarantee that the
IAC event occurs at the execution of this instruction
2.10.2 Execution Synchronization
For completeness, consider the definition of execution synchronizing as it relates to context
synchronization. Execution synchronization is architecturally a subset of context synchronization.
Execution synchronization guarantees that the following requirement is met:
All instructions that
precede
an execution synchronizing operation must complete in the context
that existed
before
the execution synchronizing operation.
The following requirement need not be met:
All instructions that
follow
an execution synchronizing operation must complete in the context that
exists
after
the execution synchronizing operation.
Execution synchronization ensures that preceding instructions execute in the old context; subsequent
instructions might execute in either the new or old context (indeterminate). The PPC405 core provides
three execution synchronizing operations: the eieio, mtmsr, and sync instructions.
Because mtmsr is execution synchronizing, it guarantees that previous instructions complete using
the old MSR value. (For example, using mtmsr to change the endian mode.) However, to guarantee
that subsequent instructions use the new MSR value, we have to insert a context synchronization
operation, such as isync.
Note that the PowerPC Architecture requires MSR[EE] (the external interrupt bit) to be, in effect,
execution synchronizing: if a mtmsr sets MSR[EE] = 1, and an external interrupt is pending, the
exception must be taken before the instruction that follows mtmsr is executed. However, the mtmsr
instruction is not a context synchronizing operation, so the PPC405 core does not, for example,
discard prefetched instructions and refetch. Note that the wrtee and wrteei instructions can change
the value of MSR[EE], but are not execution synchronizing.
Finally, while sync and eieio are execution synchronizing, they are also more restrictive in their
requirement of memory ordering. Stating that an operation is execution synchronizing does not imply
storage ordering. This is an additional specific requirement of sync and eieio.
2.10.3 Storage Synchronization
The sync instruction guarantees that all previous storage references complete with respect to the
PPC405 core before the sync instruction completes (therefore, before any subsequent instructions
begin to execute). The sync instruction is execution synchronizing.
Consider the following use of sync: