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9-54 PPC405 Core User’s Manual
dcbz
Data Cache Block Set to Zero
dcbz
Data Cache Block Set to Zero
EA ← (RA|0) + (RB)
DCBZ(EA)
An effective address (EA) is formed by adding an index to a base address. The index is the contents
of register RB. The base address is 0 if the RA field is 0 and is the contents of register RA otherwise.
If the data block at the EA is in the data cache and the EA is marked as cachable and non-write-
through, the data in the cache block is set to 0.
If the data block at the EA is not in the data cache and the EA is marked as cachable and non-write-
through, a cache block is established and set to 0. Note that nothing is read from main storage, as
described in the programming note.
If the data block at the EA is marked as either write-through or as non-cachable, an alignment
exception occurs.
If instruction bit 31 contains 1, the contents of CR[CR0] are undefined.
Registers Altered
• None
Invalid Instruction Forms
• Reserved fields
Programming Notes
Because dcbz can establish an address in the data cache without copying the contents of that
address from main storage, the address established may be invalid with respect to the storage
subsystem. A subsequent operation may cause the address to be copied back to main storage, for
example, to make room for a new cache block; a machine check exception could occur under these
circumstances.
If dcbz is attempted to an EA which is marked as non-cachable, the software alignment exception
handler should emulate the instruction by storing zeros to the block in main storage. If a data block
corresponding to the EA exists in the cache, but the EA is non-cachable, stores (including dcbz) to
that address are considered programming errors (the cache block should previously have been
flushed).
If the EA is marked as write-through, the software alignment exception handler should emulate the
instruction by storing zeros to the block in main storage. An EA that is marked as write-through
required should also be marked as cachable; when dcbz is attempted to such an address, the
alignment exception handler should maintain coherency of cache and memory.
dcbz RA, RB
31 RA RB 1014
0 6 11 16 21 31