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xvi PPC405 Core User’s Manual
Figure 8-3. Debug Status Register (DBSR) .................................................................................................... 8-8
Figure 8-4. Instruction Address Compare Registers (IAC1–IAC4) ................................................................. 8-9
Figure 8-5. Data Address Compare Registers (DAC1–DAC2) ..................................................................... 8-10
Figure 8-6. Data Value Compare Registers (DVC1–DVC2) ......................................................................... 8-10
Figure 8-7. Inclusive IAC Range Address Compares ................................................................................... 8-13
Figure 8-8. Exclusive IAC Range Address Compares .................................................................................. 8-13
Figure 8-9. Inclusive DAC Range Address Compares ................................................................................. 8-15
Figure 8-10. Exclusive DAC Range Address Compares .............................................................................. 8-15
Figure 8-11. JTAG Connector Physical Layout (Top View) .......................................................................... 8-20
Figure 10-1. Core Configuration Register 0 (CCR0) .................................................................................... 10-6
Figure 10-2. Condition Register (CR) ........................................................................................................... 10-8
Figure 10-3. Count Register (CTR) .............................................................................................................. 10-9
Figure 10-4. Data Address Compare Registers (DAC1–DAC2) ................................................................. 10-10
Figure 10-5. Debug Control Register 0 (DBCR0) ....................................................................................... 10-11
Figure 10-6. Debug Control Register 1 (DBCR1) ....................................................................................... 10-13
Figure 10-7. Debug Status Register (DBSR) .............................................................................................. 10-15
Figure 10-8. Data Cache Cachability Register (DCCR) ............................................................................. 10-17
Figure 10-9. Data Cache Write-through Register (DCWR) ........................................................................ 10-19
Figure 10-10. Data Exception Address Register (DEAR) ........................................................................... 10-21
Figure 10-11. Data Value Compare Registers (DVC1–DVC2) ................................................................... 10-22
Figure 10-12. Exception Syndrome Register (ESR) ................................................................................... 10-23
Figure 10-13. Exception Vector Prefix Register (EVPR) ............................................................................ 10-25
Figure 10-14. General Purpose Registers (R0-R31) .................................................................................. 10-26
Figure 10-15. Instruction Address Compare Registers (IAC1–IAC4) ......................................................... 10-27
Figure 10-16. Instruction Cache Cachability Register (ICCR) .................................................................... 10-28
Figure 10-17. Instruction Cache Debug Data Register (ICDBDR) ............................................................. 10-30
Figure 10-18. Link Register (LR) ................................................................................................................ 10-31
Figure 10-19. Machine State Register (MSR) ............................................................................................ 10-32
Figure 10-20. Process ID (PID) .................................................................................................................. 10-34
Figure 10-21. Programmable Interval Timer (PIT) ...................................................................................... 10-35
Figure 10-22. Processor Version Register (PVR) ....................................................................................... 10-36
Figure 10-23. Storage Guarded Register (SGR) ........................................................................................ 10-37
Figure 10-24. Storage Little-Endian Register (SLER) ................................................................................ 10-39
Figure 10-25. Special Purpose Registers General (SPRG0–SPRG7) ....................................................... 10-41
Figure 10-26. Save/Restore Register 0 (SRR0) ......................................................................................... 10-42
Figure 10-27. Save/Restore Register 1 (SRR1) ......................................................................................... 10-43
Figure 10-28. Save/Restore Register 2 (SRR2) ......................................................................................... 10-44
Figure 10-29. Save/Restore Register 3 (SRR3) ......................................................................................... 10-45
Figure 10-30. Storage User-defined 0 Register (SU0R) ............................................................................. 10-46
Figure 10-31. Time Base Lower (TBL) ....................................................................................................... 10-48
Figure 10-32. Time Base Upper (TBU) ....................................................................................................... 10-49
Figure 10-33. Timer Control Register (TCR) .............................................................................................. 10-50
Figure 10-34. Timer Status Register (TSR) ................................................................................................ 10-51
Figure 10-35. User SPR General 0 (USPRG0) .......................................................................................... 10-52
Figure 10-36. Fixed Point Exception Register (XER) ................................................................................. 10-53
Figure 10-37. Zone Protection Register (ZPR) ........................................................................................... 10-54