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Instruction Set 9-53
dcbtst
Data Cache Block Touch for Store
dcbtst
Data Cache Block Touch for Store
EA ← (RA|0) + (RB)
DCBTST(EA)
An effective address (EA) is formed by adding an index to a base address. The index is the contents
of register RB. The base address is 0 if the RA field is 0 and is the contents of register RA otherwise.
If the data block at the EA is not in the data cache and the EA address is marked as cachable, the
data block is loaded into the data cache.
If the EA is marked as non-cachable, or if the data block at the EA is in the data cache, no operation
is performed.
This instruction is not allowed to cause data storage exceptions or data TLB miss exceptions. If
execution of the instruction would cause such an exception, then no operation is performed, and no
exception occurs.
If instruction bit 31 contains 1, the contents of CR[CR0] are undefined.
Registers Altered
• None
Invalid Instruction Forms
• Reserved fields
Programming Notes
The dcbtst instruction allows a program to begin a cache block fetch from main storage before the
program needs the data. The program can later store data from GPRs into the cache block, without
incurring the latency of a cache miss.
Architecturally, dcbtst brings data into the cache in “Exclusive” mode, which allows the program to
alter the cached data. “Exclusive” mode is part of the MESI protocol for multi-processor systems, and
is not implemented. The implementation of the dcbtst instruction is identical to the implementation of
the dcbt instruction.
Exceptions
This instruction is considered a “load” with respect to data storage exceptions. See “Data Storage
Interrupt” on page 5-16.
This instruction is considered a “load” with respect to data address compare (DAC) debug exceptions.
See “Debug Interrupt” on page 5-26.
Architecture Note
This instruction is part of the IBM PowerPC Embedded Virtual Environment.
dcbtst RA, RB
31 RA RB 246
0 6 11 16 21 31