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Initialization 3-1
Chapter 3. Initialization
This chapter describes reset operations, the initial state of the PPC405 core after a reset, and an
example of the initialization code required to begin executing application code. Initialization of external
system components or system-specific chip facilities may also be performed, in addition to the basic
initialization described in this chapter.
Reset operations affect the PPC405 at power on time as well as during normal operation, if
programmed to do so. To understand how these operations work it is necessary to first understand
the signal pins involved as well as the terminology of core, chip and system resets.Three types of
reset, each with different scope, are possible in the PPC405. A core reset affects only the processor
core. Chip resets affect the processor core and all on-chip peripherals. System resets affect the
processor core, all on-chip peripherals, and any off-chip devices connected to the chip reset net. Only
the processor core can request a core or chip reset.
The processor core can request three types of processor resets: core, chip, and system. Each type of
reset can be generated by a JTAG debug tool, by the second expiration of the watchdog timer, or by
writing a non-zero value to the Reset (RST) field of Debug Control Register 0 (DBCR0). In
Core+ASIC and system on chip (SOC) designs, reset signals from on-chip and external peripherals
can initiate system resets.
The effects of core and chip resets on the processor core are identical. To determine which reset type
occurred, the most-recent reset (MRR) field of the Debug Status Register (DBSR) can be examined.
3.1 Processor State After Reset
After a reset, the contents of the Machine State Register (MSR) and the Special Purpose Registers
(SPRs) control the initial processor state. The contents of Device Control Registers (DCRs) control
the initial states of on-chip devices. Chapter 10, “Register Summary,” contains descriptions of the
registers.
In general, the contents of SPRs are undefined after a reset. Reset initializes the minimum number of
SPR fields required for allow successful instruction fetching. “Contents of Special Purpose Registers
after Reset” on page 3-3 describes these initial values. System software fully configures the
processor.
“Machine State Register Contents after Reset” on page 3-2 describes the MSR contents.
The MCI field of the Exception Syndrome Register (ESR) is cleared so that it can be determined if
there has been a machine check during initialization, before machine check exceptions are enabled.
Core reset Resets the processor core, including the data cache unit (DCU) and instruction
cache unit (ICU).
Chip reset Resets the processor core, including the DCU and ICU. This type of reset is
provided in the IBM PowerPC 400 Series Embedded controllers as a means of
resetting on-chip peripherals, and is provided on the PPC405 for compatibility.
System reset Resets the entire chip. The reset signal is driven active by the PPC405 during
system reset.