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9-88 PPC405 Core User’s Manual
lswx
Load String Word Indexed
Invalid Instruction Forms
• Reserved fields
• RA or RB is in the range of registers to be loaded.
• RA=RT=0
Programming Note
If XER[TBC] = 0, the contents of register RT are unchanged and lswx is treated as a no-op.
The PowerPC Architecture states that, if XER[TBC] = 0 and if the EA is such that a precise data
exception would normally occur (if not for the zero length), lswx is treated as a no-op and the precise
exception will not occur. Data storage exceptions and alignment exceptions are examples of precise
data exceptions.
However, the PowerPC Architecture makes no statement regarding imprecise exceptions related to
lswx with XER[TBC] = 0. The PPC405 core generates an imprecise exception (machine check) on
this instruction when all of the following conditions are true:
• The instruction passes all protection bounds checking
• The address is cachable
• The address is passed to the data cache
• The address misses in the data cache (resulting in a line fill request)
• The address encounters some form of bus error
Architecture Note
This instruction is part of the PowerPC User Instruction Set Architecture.