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Instruction Set 9-193
twi
Trap Word Immediate
twi
Trap Word Immediate
if ( ((RA) EXTS(IM) ∧ TO
0
=1) ∨
((RA) EXTS(IM)
∧ TO
1
=1) ∨
((RA) EXTS(IM)
∧ TO
2
=1) ∨
((RA) EXTS(IM)
∧ TO
3
=1) ∨
((RA) EXTS(IM)
∧ TO
4
= 1) ) then TRAP (see details below)
Register RA is compared with the IM field, which has been sign-extended to 32 bits. If any
comparison condition selected by the TO field is true, a TRAP occurs. The behavior of a TRAP
depends upon the Debug Mode of the processor, as described below:
• If TRAP is not enabled as a debug event (DBCR[TDE] = 0 or DBCR[EDM,IDM] = 0,0):
TRAP causes a program interrupt. See “Program Interrupt” on page 5-20.
(SRR0) ← address of twi instruction
(SRR1)
← (MSR)
(ESR[PTR])
← 1
(MSR[WE, EE, PR, DR, IR])
← 0
PC
← EVPR
0:15
|| 0x0700
• If TRAP is enabled as an External debug event (DBCR[TDE] = 1 and DBCR[EDM] = 1):
TRAP goes to the Debug Stop state, to be handled by an external debugger with hardware control
of the PPC405 core.
(DBSR[TIE]) ← 1
In addition, if TRAP is also enabled as an Internal debug event (DBCR[IDM] = 1)
and Debug Exceptions are disabled (MSR[DE] = 0), then report an imprecise event:
(DBSR[IDE])
← 1
PC
← address of twi instruction
• If TRAP is enabled as an Internal debug event and
not
an External debug event (DBCR[TDE] = 1
and DBCR[EDM,IDM] = 0,1) and Debug Exceptions are enabled (MSR[DE] = 1):
TRAP causes a Debug interrupt. See “Debug Interrupt” on page 5-26.
(SRR2) ← address of twi instruction
(SRR3)
← (MSR)
(DBSR[TIE])
← 1
(MSR[WE, EE, PR, CE, DE, DR, IR])
← 0
PC
← EVPR
0:15
|| 0x2000
• If TRAP is enabled as an Internal debug event and
not
an External debug event (DBCR[TDE] = 1
and DBCR[EDM,IDM] = 0,1) and Debug Exceptions are disabled (MSR[DE] = 0):
TRAP will report the debug event as an
imprecise
event and will cause a Program interrupt. See
“Program Interrupt” on page 5-20.
twi TO, RA, IM
3TORA IM
0 6 11 16 31
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