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xviii PPC405 Core User’s Manual
Tables
Table 2-1. PPC405 SPRs ................................................................................................................................ 2-6
Table 2-2. XER[CA] Updating Instructions ...................................................................................................... 2-9
Table 2-3. XER[SO,OV] Updating Instructions ................................................................................................ 2-9
Table 2-4. Time Base Registers..................................................................................................................... 2-13
Table 2-5. Alignment Exception Summary .................................................................................................... 2-17
Table 2-6. Bits of the BO Field ...................................................................................................................... 2-25
Table 2-7. Conditional Branch BO Field ........................................................................................................ 2-26
Table 2-8. Example Memory Mapping............................................................................................................ 2-30
Table 2-9. Privileged Instructions .................................................................................................................. 2-31
Table 2-10. PPC405 Instruction Set Summary............................................................................................... 2-36
Table 2-11. Implementation-specific Instructions ........................................................................................... 2-37
Table 2-12. Storage Reference Instructions .................................................................................................. 2-37
Table 2-13. Arithmetic Instructions ................................................................................................................ 2-38
Table 2-14. Multiply-Accumulate and Multiply Halfword Instructions ............................................................. 2-39
Table 2-15. Logical Instructions ..................................................................................................................... 2-39
Table 2-16. Compare Instructions ................................................................................................................. 2-39
Table 2-17. Branch Instructions ..................................................................................................................... 2-40
Table 2-18. CR Logical Instructions .............................................................................................................. 2-40
Table 2-19. Rotate Instructions ..................................................................................................................... 2-40
Table 2-20. Shift Instructions ......................................................................................................................... 2-41
Table 2-21. Cache Management Instructions ................................................................................................ 2-41
Table 2-22. Interrupt Control Instructions ...................................................................................................... 2-41
Table 2-23. TLB Management Instructions ................................................................................................... 2-42
Table 2-24. Processor Management Instructions .......................................................................................... 2-42
Table 3-1. MSR Contents after Reset .............................................................................................................. 3-2
Table 3-2. SPR Contents After Reset .............................................................................................................. 3-3
Table 4-1. Available Cache Array Sizes........................................................................................................... 4-2
Table 4-2. ICU and DCU Cache Array Organization........................................................................................ 4-3
Table 4-3. Cache Sizes, Tag Fields, and Lines................................................................................................ 4-3
Table 4-4. Priority Changes With Different Data Cache Operations .............................................................. 4-17
Table 5-1. Interrupt Handling Priorities ............................................................................................................ 5-4
Table 5-2. Interrupt Vector Offsets .................................................................................................................. 5-6
Table 5-3. ESR Alteration by Various Interrupts ............................................................................................ 5-13
Table 5-4. Register Settings during Critical Input Interrupts .......................................................................... 5-14
Table 5-5. Register Settings during Machine Check—Instruction Interrupts ................................................. 5-15
Table 5-6. Register Settings during Machine Check—Data Interrupts .......................................................... 5-15
Table 5-7. Register Settings during Data Storage Interrupts ......................................................................... 5-17
Table 5-8. Register Settings during Instruction Storage Interrupts ................................................................ 5-18
Table 5-9. Register Settings during External Interrupts ................................................................................. 5-19
Table 5-10. Alignment Interrupt Summary ..................................................................................................... 5-19
Table 5-11. Register Settings during Alignment Interrupts ............................................................................ 5-19
Table 5-12. ESR Usage for Program Interrupts ............................................................................................ 5-20