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3-6 PPC405 Core User’s Manual
mtspr(EVPR, prefix_addr); /* initialize exception vector prefix */
/* Initialize vector table and interrupt handlers if not already done */
/* Initialize and configure timer facilities */
mtspr(PIT, 0); /* clear PIT so no PIT indication after TSR cleared*/
mtspr(TSR, 0xFFFFFFFF); /* clear TSR */
mtspr(TCR, timer_enable); /* enable desired timers */
mtspr(TBL, 0); /* reset time base low first to avoid ripple */
mtspr(TBU, time_base_u); /* set time base, hi first to catch possible ripple */
mtspr(TBL, time_base_l); /* set time base, low */
mtspr(PIT, pit_count); /* set desired PIT count */
/* Initialize the MSR */
/*———————————————————————————————————— */
/* Exceptions must be enabled immediately after timer facilities to avoid missing a */
/* timer exception. */
/* */
/* The MSR also controls privileged/user mode, translation, and the wait state. */
/* These must be initialized by the operating system or application code. */
/* If enabling translation, code must initialize the TLB. */
/*———————————————————————————————————— */
mtmsr(machine_state);
/*———————————————————————————————————— */
/* Initialization of other processor facilities should be performed at this time. */
/*———————————————————————————————————— */
/*———————————————————————————————————— */
/* Initialization of non-processor facilities should be performed at this time. */
/*———————————————————————————————————— */
/*———————————————————————————————————— */
/* Branch to operating system or application code can occur at this time. */
/*———————————————————————————————————— */