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A-16 PPC405 Core User’s Manual
isync Synchronize execution context by flushing the prefetch
queue.
9-70
la RT, D(RA) Load address. (RA ≠ 0)
D is an offset from a base address that is assumed to
be (RA).
(RT)
← (RA) + EXTS(D)
Extended mnemonic for
addi RT,RA,D
9-9
lbz RT, D(RA) Load byte from EA = (RA|0) + EXTS(D) and pad left
with zeroes,
(RT)
←
24
0 || MS(EA,1).
9-71
lbzu RT, D(RA) Load byte from EA = (RA|0) + EXTS(D) and pad left
with zeroes,
(RT)
←
24
0 || MS(EA,1).
Update the base address,
(RA)
← EA.
9-72
lbzux RT, RA, RB Load byte from EA = (RA|0) + (RB) and pad left with
zeroes,
(RT)
←
24
0 || MS(EA,1).
Update the base address,
(RA)
← EA.
9-73
lbzx RT, RA, RB Load byte from EA = (RA|0) + (RB) and pad left with
zeroes,
(RT)
←
24
0 || MS(EA,1).
9-74
lha RT, D(RA) Load halfword from EA = (RA|0) + EXTS(D) and sign
extend,
(RT)
← EXTS(MS(EA,2)).
9-75
lhau RT, D(RA) Load halfword from EA = (RA|0) + EXTS(D) and sign
extend,
(RT)
← EXTS(MS(EA,2)).
Update the base address,
(RA)
← EA.
9-76
lhaux RT, RA, RB Load halfword from EA = (RA|0) + (RB) and sign
extend,
(RT)
← EXTS(MS(EA,2)).
Update the base address,
(RA)
← EA.
9-77
lhax RT, RA, RB Load halfword from EA = (RA|0) + (RB) and sign
extend,
(RT)
← EXTS(MS(EA,2)).
9-78
lhbrx RT, RA, RB Load halfword from EA = (RA|0) + (RB), then reverse
byte order and pad left with zeroes,
(RT)
←
16
0 || MS(EA+1,1) || MS(EA,1).
9-79
lhz RT, D(RA) Load halfword from EA = (RA|0) + EXTS(D) and pad
left with zeroes,
(RT)
←
16
0 || MS(EA,2).
9-80
Table A-1. PPC405 Instruction Syntax Summary (continued)
Mnemonic Operands Function
Other Registers
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