Filter
Top Products
3-4 PPC405 Core User’s Manual
Because the processor is initially in big endian mode, initialization code must be in big endian format
until the endian storage attribute for the addressed region is changed, or until code branches to a
region defined as little endian storage.
Before a reset operation begins, the system must provide non-volatile memory, or memory initialized
by some mechanism external to the processor. This memory must be located at address
0xFFFFFFFC.
3.3 Initialization Requirements
When any reset is performed, the processor is initialized to a minimum configuration to start executing
initialization code. Initialization code is necessary to complete the processor and system
configuration.
The initialization code example in this section performs the configuration tasks required to prepare the
PPC405 core to boot an operating system or run an application program.
Some portions of the initialization code work with system components that are beyond the scope of
this manual.
Initialization code should perform the following tasks to configure the processor resources.
To improve instruction fetching performance: initialize the SGR appropriately for guarded or
unguarded storage. Since all storage is initially guarded and speculative fetching is inhibited to
guarded storage, reprogramming the SGR will improve performance for unguarded regions.
1. Before executing instructions as cachable:
– Invalidate the instruction cache.
– Initialize the ICCR to configure instruction cachability.
2. Before using storage access instructions:
– Invalidate the data cache.
– Initialize CRRO to determine if a store miss results in a line fill (SWOA).
– Initialize the DCWR to select copy-back or write-through caching.
– Initialize the DCCR to configure data cachability.
3. Before allowing interrupts (synchronous or asynchronous):
– Initialize the EVPR to point to vector table.
– Provide vector table with branches to interrupt handlers.
4. Before enabling asynchronous interrupts:
– Initialize timer facilities.
– Initialize MSR to enable appropriate interrupts.
5. Initialize other processor features, such as the MMU, APU (if implemented), debug, and trace.
6. Initialize non-processor resources.
– Initialize system memory as required by the operating system or application code.
– Initialize off-chip system facilities.
7. Start the execution of operating system or application code.