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Instruction Set 9-69
icread
Instruction Cache Read
The instruction pipeline does not automatically wait for data from icread to arrive at the ICDBDR
before attempting to use the contents of the ICDBDR. Therefore, insert an isync instruction between
icread and mficdbdr.
icread r5,r6 # read cache information
isync # ensure completion of icread
mficdbdr r7 # move information to GPR
Instruction cache operations use MSR[DR], not MSR[IR], to determine translation of their operands.
When data translation is disabled, cachability for the EA of the operand of instruction cache
operations is determined by the ICCR, not the DCCR.
Exceptions
Instruction storage exceptions and instruction-side TLB miss exceptions are associated with
instruction
fetching
, not with instruction execution. Exceptions that occur during the
execution
of
instruction cache operations cause data-side exceptions (data storage exceptions and data TLB miss
exceptions).
The execution of icread can cause a data TLB miss exception, at the specified EA, regardless of the
non-specific intent of that EA.
This instruction is considered a “load” and cannot cause a data storage exception.
This instruction is considered a “load” with respect to data address compare (DAC) debug exceptions,
but will not cause DAC debug events.
Architecture Note
This instruction is implementation-specific and may not be portable to other implementations.