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2-34 PPC405 Core User’s Manual
In this sequence, the isync instruction does not guarantee that the XYZ instruction is fetched after
the STORE has occurred to memory. There is no guarantee which XYZ instruction will execute;
either the old version or the new (stored) version might.
2. Consider the following instruction sequence, which assumes that a PPC405 core is part of a
standard product that uses DCRs to provide bus region control:
STORE non-cachable to address XYZ
isync
MTDCR to change a bus region containing XYZ
In this sequence, there is no guarantee that the STORE will occur before the mtdcr changing the
bus region control DCR. The STORE could fail because of a configuration error.
Consider an interrupt that changes privileged mode. An interrupt is a context synchronizing operation,
because interrupts cause the MSR to be updated. The MSR is part of the processor context; the
context synchronizing operation guarantees that all instructions that precede the interrupt complete
using the preinterrupt value of MSR[PR], and that all instructions that follow the interrupt complete
using the postinterrupt value.
Consider, on the other hand, some code that uses mtmsr to change the value of MSR[PR], which
changes the privileged mode. In this case, the MSR is changed, changing the context. It is possible,
for example, that prefetched privileged instructions expect to execute after the mtmsr has changed
the operating mode from privileged mode to user mode. To prevent privileged instruction program
exceptions, the code must execute a context synchronization operation, such as isync, immediately
after the mtmsr instruction to prevent further instruction execution until the mtmsr completes.
eieio or sync can ensure that the contents of memory and DCRs are synchronized in the instruction
stream. These instructions guarantee storage ordering because all memory accesses that precede
eieio or sync are completed before subsequent memory accesses. Neither eieio nor sync guarantee
that instruction prefetching is delayed until the eieio or sync completes. The instructions do not cause
the prefetch queues to be purged and instructions to be refetched. See “Storage Synchronization” on
page 2-35 for more information.
Instruction cache state is part of context. A context synchronization operation is required to guarantee
instruction cache access ordering.
3. Consider the following instruction sequence, which is required for creating self-modifying code:
STORE Change data cache contents
dcbst Flush the new data cache contents to memory
sync Guarantee that dcbst completes before subsequent instructions begin
icbi Context changing operation; invalidates instruction cache contents.
isync Context synchronizing operation; causes refetch using new instruction cache context
text and new memory context, due to the previous sync.
If software wishes to ensure that all storage accesses are complete before executing a mtdcr to
change a bus region (Example 2), the software must issue a sync after all storage accesses and
before the mtdcr. Likewise, if the software is to ensure that all instruction fetches after the mtdcr use
the new bank register contents, the software must issue an isync, after the mtdcr and before the first
instruction that should be fetched in the new context.