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Overview 1-1
Chapter 1. Overview
The IBM 405 32-bit reduced instruction set computer (RISC) processor core, referred to as the
PPC405 core, implements the PowerPC Architecture with extensions for embedded applications.
This chapter describes:
• PPC405 core features
• The PowerPC Architecture
• The PPC405 implementation of the IBM PowerPC Embedded Environment, an extension of the
PowerPC Architecture for embedded applications
• PPC405 organization, including a block diagram and descriptions of the functional units
• PPC405 registers
• PPC405 addressing modes
1.1 PPC405 Features
The PPC405 core provides high performance and low power consumption. The PPC405 RISC CPU
executes at sustained speeds approaching one cycle per instruction. On-chip instruction and data
caches arrays can be implemented to reduce chip count and design complexity in systems and
improve system throughput.
The PowerPC RISC fixed-point CPU features:
• PowerPC User Instruction Set Architecture (UISA) and extensions for embedded applications
• Thirty-two 32-bit general purpose registers (GPRs)
• Static branch prediction
• Five-stage pipeline with single-cycle execution of most instructions, including loads/stores
• Unaligned load/store support to cache arrays, main memory, and on-chip memory (OCM)
• Hardware multiply/divide for faster integer arithmetic (4-cycle multiply, 35-cycle divide)
• Multiply-accumulate instructions
• Enhanced string and multiple-word handling
• True little endian operation
• Programmable Interval Timer (PIT), Fixed Interval Timer (FIT), and watchdog timer
• Forward and reverse trace from a trigger event
• Storage control
– Separate, configurable, two-way set-associative instruction and data cache units; for the
PPC405B3, the instruction cache array is 16KB and the data cache array is 8KB
– Eight words (32 bytes) per cache line
– Support for any combination of 0KB, 4KB, 8KB, and 16KB, and 32KB instruction and data cache
arrays, depending on model