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6-8 PPC405 Core User’s Manual
To clear TSR[ENW], use mtspr to write a 1 to TSR[ENW] (and to any other bits that are to be
cleared), with 0 in all other bit locations.
b. Clear TSR[WIS] in watchdog timer handler.
It is not expected that a watchdog interrupt will occur every time, but only if an exceptionally
high execution load delays clearing of TSR[ENW] in the usual time frame.
3. Never take a watchdog interrupt.
This assumes that a recurring code loop of reliable duration exists outside the interrupt handlers, or
that a FIT interrupt handler is operational. This method only guarantees one watchdog timeout
period before a reset occurs.
a. Clear TSR[WIS] in the loop or in FIT handler.
b. Never use TSR[ENW] but have it set.
6.4 Timer Status Register (TSR)
The TSR can be accessed for read or write-to-clear.
Status registers are generally set by hardware and read and cleared by software. The mfspr
instruction reads the TSR. Clearing the TSR is performed by writing a word to the TSR, using mtspr,
havinga1inallfields to be cleared anda0inallother fields. The data written to the TSR is not direct
data, but a mask. A 1 clears the field and a 0 has no effect.
Figure 6-6. Timer Status Register (TSR)
0 ENW Enable Next Watchdog
0 Action on next watchdog event is to set
TSR[ENW] = 1.
1 Action on next watchdog event is
governed by TSR[WIS].
Software must reset TSR[ENW] = 0 after
each watchdog timer event.
1 WIS Watchdog Interrupt Status
0 No Watchdog interrupt is pending.
1 Watchdog interrupt is pending.
2:3 WRS Watchdog Reset Status
00 No Watchdog reset has occurred.
01 Core reset was forced by the watchdog.
10 Chip reset was forced by the watchdog.
11 System reset was forced by the
watchdog.
4 PIS PIT Interrupt Status
0 No PIT interrupt is pending.
1 PIT interrupt is pending.
0123456 31
ENW
WIS
WRS FIS
PIS