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2-12 PPC405 Core User’s Manual
compares, the values are considered to be signed, where 31 bits represent the magnitude and the
most-significant bit is a sign bit. For
logical
compares, the values are considered to be unsigned, so
all 32 bits represent magnitude. There is no sign bit. As an example, consider the comparison of 0
with 0xFFFFFFFF. In an
arithmetic
compare, 0 is larger, because 0xFFFF FFFF represents –1; in a
logical
compare, 0xFFFFFFFF is larger.
A compare instruction can direct its CR update to any CR field. The first data operand of a compare
instruction specifies a GPR. The second data operand specifies another GPR, or immediate data
derived from the IM field of the immediate instruction form. The contents of the GPR specified by the
first data operand are compared with the contents of the GPR specified by the second data operand
(or with the immediate data). See descriptions of the compare instructions (page 9-34 through
page 9-37) for precise details.
After a compare, the specified CR field is interpreted as follows:
2.3.3.2 The CR0 Field
After the execution of compare instructions that update CR[CR0], CR[CR0] is interpreted as
described in “CR Fields after Compare Instructions” on page 2-11. The “dot” forms of arithmetic and
logical instructions also alter CR[CR0]. After most instructions that update CR[CR0], the bits of CR0
are interpreted as follows:
The CR[CR0]
LT, GT, EQ
subfields are set as the result of an algebraic comparison of the instruction
result to 0, regardless of the type of instruction that sets CR[CR0]. If the instruction result is 0, the EQ
subfield is set to 1. If the result is not 0, either LT or GT is set, depending on the value of the most-
significant bit of the result.
When updating CR[CR0], the most significant bit of an instruction result is considered a sign bit, even
for instructions that produce results that are not usually thought of as signed. For example, logical
instructions such as and., or., and nor. update CR[CR0]
LT, G T, EQ
using such an arithmetic comparison
to 0, although the result of such a logical operation is not actually an arithmetic result.
If an arithmetic overflow occurs, the “sign” of an instruction result indicated in CR[CR0]
LT, GT, EQ
might
not represent the “true” (infinitely precise) algebraic result of the instruction that set CR0. For
example, if an add. instruction adds two large positive numbers and the magnitude of the result
cannot be represented as a twos-complement number in a 32-bit register, an overflow occurs and
CR[CR0]
LT, SO
are set, although the infinitely precise result of the add is positive.
LT (bit 0) The first operand is less than the second operand.
GT (bit 1) The first operand is greater than the second operand.
EQ (bit 2) The first operand is equal to the second operand.
SO (bit 3) Summary overflow; a copy of XER[SO].
LT (bit 0) Less than 0; set if the most-significant bit of the 32-bit result is 1.
GT (bit 1)
Greater than 0; set if the 32-bit result is non-zero and the most-
significant bit of the result is 0.
EQ (bit 2) Equal to 0; set if the 32-bit result is 0.
SO (bit 3) Summary overflow; a copy of XER[SO] at instruction completion.