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5-6 PPC405 Core User’s Manual
written by the time of the interrupt; when the instruction restarts, the registers will simply be written
again. Similarly, some of the target memory of a store instruction may have been written, and is
written again when the instruction restarts.
Save/Restore Register 1 (SRR1) is written with the contents of the MSR; the MSR is then updated to
reflect the new machine context. The new MSR contents take effect beginning with the first instruction
of the interrupt handling routine.
Interrupt handling routine instructions are fetched at an address determined by the interrupt type. The
address of the interrupt handling routine is formed by concatenating the 16 high-order bits of the
EVPR and the interrupt vector offset. (A user must initialize the EVPR contents at power-up using an
mtspr instruction.)
Table 5-2 shows the interrupt vector offsets for the interrupt types. Note that there can be multiple
sources of the same interrupt type; interrupts of the same type are mapped to the same interrupt
vector, regardless of source. In such cases, the interrupt handling routine must examine status
registers to determine the exact source of the interrupt.
At the end of the interrupt handling routine, execution of an rfi instruction forces the contents of SRR0
and SRR1 to be written to the program counter and the MSR, respectively. Execution then begins at
the address in the program counter.
Critical interrupts are processed similarly. When a critical interrupt is taken, Save/Restore
Register 2 (SRR2) and Save/Restore Register 3 (SRR3) hold the next sequential address to be
processed when returning from the interrupt, and the contents of the MSR, respectively. At the end of
the critical interrupt handling routine, execution of an rfci instruction writes the contents of SRR2 and
SRR3 into the program counter and the MSR, respectively.
Table 5-2. Interrupt Vector Offsets
Offset Interrupt Type Interrupt Class Category Page
0x0100 Critical input interrupt Asynchronous precise Critical 5-13
0x0200 Machine check—data — Critical 5-14
Machine check—instruction — Critical 5-14
0x0300 Data storage interrupt—
MSR[DR]=1 and
ZPR[Z
n
]=0 or
TLB_entry[WR] = 0 or
TLB_entry[U0] = 1 or
SU0R[U
n
]=1
Synchronous precise Noncritical 5-16
0x0400 Instruction storage interrupt Synchronous precise Noncritical 5-17
0x0500 External interrupt Asynchronous precise Noncritical 5-18
0x0600 Alignment Synchronous precise Noncritical 5-19
0x0700 Program Synchronous precise Noncritical 5-20
0x0800 FPU Unavailable Synchronous precise Noncritical 5-21
0x0C00 System Call Synchronous precise Noncritical 5-22
0x0F20 APU Unavailable Synchronous precise Noncritical 5-22
0x1000 PIT Asynchronous precise Noncritical 5-22
0x1010 FIT Asynchronous precise Noncritical 5-23
0x1020 Watchdog timer Asynchronous precise Critical 5-24
0x1100 Data TLB miss Synchronous precise Noncritical 5-25