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5-20 PPC405 Core User’s Manual
5.12 Program Interrupt
Program interrupts are caused by attempting to execute:
• An illegal instruction
• A privileged instruction while in the problem state
• Executing a trap instruction with conditions satisfied
• An unimplemented APU or FPU instruction
• An APU instruction with APU interrupt enabled
• An FPU instruction with FPU interrupt enabled
The ESR bits that differentiate these situations are listed and described in Table 5-12. When a
program interrupt occurs, the appropriate bit is set and the others are cleared. These interrupts are
not maskable.
The program interrupt handler does not need to reset the ESR.
When one of the following occurs, the PPC405 does not execute the instruction, but writes the
address of the excepting instruction into SRR0:
• Attempted execution of a privileged instruction in problem state
• Attempted execution of an illegal instruction (including memory management instructions when
memory management is disabled or when TIEc405MmuEn = 0.
When the TIEc405MmuEn signal is tied to 0, the TLB instructions (tlbia, tlbre, tlbsx, tlbsync, and
tlbwe) are treated as illegal instructions. When execution of any of these instructions occurs under
this circumstance, a program interrupt results.Trap instructions can be used as a program interrupt or
a debug event, or both (see “Debug Events” on page 8-10 for information about debug events). When
a trap instruction is detected as a program interrupt, the PPC405 writes the address of the trap
instruction into SRR0. See tw on page 9-190 and twi on page 9-193 (both in Chapter 9, “Instruction
Set”) for a detailed discussion of the behavior of trap instructions with various interrupts enabled.
PC EVPR[0:15] || 0x0600
DEAR Written with the address that caused the alignment violation
Table 5-12. ESR Usage for Program Interrupts
Bits Interrupts Cause
ESR[PIL] Illegal instruction Opcode not recognized
ESR[PPR] Privileged instruction Attempt to use a privileged instruction in the problem state
ESR[PTR] Trap Excepting instruction is a trap
ESR[PEU] Unimplemented An FPU or APU instruction is unimplemented
ESR[PFP] FPU Excepting instruction is an FPU instruction
ESR[PAP] APU Excepting instruction is an APU instruction
Table 5-11. Register Settings during Alignment Interrupts (continued)