Filter
Top Products
Index X-3
bunl 9-25
bunla 9-25
bunlr 9-33
bunlrl 9-33
byte ordering
big endian, defined 2-18
little endian
defined 2-18
supported 2-19
overview 2-17
byte reversal
during load/store access 2-21
byte-reverse instructions
augmented by endian (E) storage attribute 2-23
compare to endian (E) storage attribute 2-21
C
cache
instructions
DAC debug events 8-15
cache block, defined 4-9
cache control instructions
access protection 7-16
causing data storage interrupts 7-16
cache line
dirty, defined 4-16
See also
cache block
cache line fills
DCU 4-6
defined 4-6
types 4-4
caches.
See
ICU;DCU
caching inhibited (I) storage attribute
for data accesses, controlled by DCCR 7-20
for instruction fetches, controlled by ICCR 7-20
virtual mode 7-5
CCR0 10-6
clrlslwi 9-147
clrlslwi. 9-147
clrlwi 9-147
clrlwi. 9-147
clrrwi 9-148
clrrwi. 9-148
cmp 9-34
cmpi 9-35
cmpl 9-36
cmpli 9-37
cmplw 9-36
cmplwi 9-37
cmpw 9-34
cmpwi 9-35
cntlzw 9-38
cntlzw. 9-38
compare instructions
arithmetic 2-11
in core, listed 2-39
effect on CR fields 2-12
logical 2-11
Condition Register.
See
CR
conditional branches
AA field 2-24
BI field 2-25
BO field 2-25
mnemonics used to control prediction 2-27
context synchronization
defined 2-33
for ITLB 7-7
limitations 2-33
context, defined 2-33
conventions
notational xxii
Count Register.
See
CTR
CR 10-8
CR (Condition Register)
arithmetic and logical instructions 2-38
compare instructions 2-11
, 2-39
CR0 field 2-12
- 2-13
logical instructions 2-39
setting fields 2-10
summarized 1-9
crand 9-39
crandc 9-40
crclr 9-46
creqv 9-41
critical input interrupts 5-13
register settings 5-14
critical interrupts 5-3
defined 5-5
processing 5-6
crmove 9-44
crnand 9-42
crnor 9-43
crnot 9-43
cror 9-44
crorc 9-45
crset 9-41
crxor 9-46
CTR 10-9
CTR (Count Register)
branch instructions 2-40
functions 2-6
testing by branch instructions 2-25
D
DAC1 8-9
DAC1–DAC2 8-9
, 10-10
Data Address Compare Register (DAC1) 8-9
data alignment
in little endian storage 2-21
overview 2-16
Data Cache Cachability Register.
See
DCCR
Data Cache Cachability Register.
See
DCCR
data cache unit.
See
DCU
Data Cache Write-through Register.
See
DCWR
Data Cache Write-through Register.
See
DCWR
Data Exception Address Register.
See
DEAR
data machine check interrupts
register settings 5-15
data storage interrupts
caused by cache control instructions 7-16
causes 5-16
described 7-10
programming note 5-16
register settings 5-17