Filter
Top Products
DBSR (cont.)
Debug Status Register
10-16 PPC405 Core User’s Manual
11 IDE Imprecise Debug Event
0 No circumstance that would cause a
debug event (if MSR[DE] = 1) occurred
1 A debug event would have occurred, but
debug exceptions were disabled
(MSR[DE] = 0)
12 IA3 IAC3 Debug Event
0 Event did not occur
1 Event occurred
13 IA4 IAC4 Debug Event
0 Event did not occur
1 Event occurred
14:21
Reserved
22:23 MRR Most Recent Reset
00 No reset has occurred since last
cleared by software.
01 Core reset
10 Chip reset
11 System reset
This field is set to a value, indicating the
type of reset, when a reset occurs.
24:31
Reserved