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Vol. 3 4-1
CHAPTER 4
PAGING
Chapter 3 explains how segmentation converts logical addresses to linear addresses.
Paging (or linear-address translation) is the process of translating linear addresses
so that they can be used to access memory or I/O devices. Paging translates each
linear address to a physical address and determines, for each translation, what
accesses to the linear address are allowed (the address’s access rights) and the
type of caching used for such accesses (the address’s memory type).
Intel-64 processors support three different paging modes. These modes are identi-
fied and defined in Section 4.1. Section 4.2 gives an overview of the translation
mechanism that is used in all modes. Section 4.3, Section 4.4, and Section 4.5
discuss the three paging modes in detail.
Section 4.6 details how paging determines and uses access rights. Section 4.7
discusses exceptions that may be generated by paging (page-fault exceptions).
Section 4.8 considers data which the processor writes in response to linear-address
accesses (accessed and dirty flags).
Section 4.9 describes how paging determines the memory types used for accesses to
linear addresses. Section 4.10 provides details of how a processor may cache infor-
mation about linear-address translation. Section 4.11 outlines interactions between
paging and certain VMX features. Section 4.12 gives an overview of how paging can
be used to implement virtual memory.
4.1 PAGING MODES AND CONTROL BITS
Paging behavior is controlled by the following control bits:
• The WP and PG flags in control register CR0 (bit 16 and bit 31, respectively).
• The PSE, PAE, and PGE flags in control register CR4 (bit 4, bit 5, and bit 7,
respectively).
• The LME and NXE flags in the IA32_EFER MSR (bit 8 and bit 11, respectively).
Software enables paging by using the MOV to CR0 instruction to set CR0.PG. Before
doing so, software should ensure that control register CR3 contains the physical
address of the first paging structure that the processor will use for linear-address
translation (see Section 4.2) and that structure is initialized as desired. See
Table 4-3, Table 4-7, and Table 4-12 for the use of CR3 in the different paging
modes.
Section 4.1.1 describes how the values of CR0.PG, CR4.PAE, and IA32_EFER.LME
determine whether paging is in use and, if so, which of three paging modes is in use.
Section 4.1.2 explains how to manage these bits to establish or make changes in