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Vol. 3 11-15
MEMORY CACHE CONTROL
11.5.1 Cache Control Registers and Bits
Figure 11-3 depicts cache-control mechanisms in IA-32 processors. Other than for
the matter of memory address space, these work the same in Intel 64 processors.
The Intel 64 and IA-32 architectures provide the following cache-control registers
and bits for use in enabling or restricting caching to various pages or regions in
memory:
• CD flag, bit 30 of control register CR0 — Controls caching of system memory
locations (see Section 2.5, “Control Registers”). If the CD flag is clear, caching is
enabled for the whole of system memory, but may be restricted for individual
pages or regions of memory by other cache-control mechanisms. When the CD
flag is set, caching is restricted in the processor’s caches (cache hierarchy) for
the P6 and more recent processor families and prevented for the Pentium
processor (see note below). With the CD flag set, however, the caches will still
respond to snoop traffic. Caches should be explicitly flushed to insure memory
coherency. For highest processor performance, both the CD and the NW flags in
control register CR0 should be cleared.
Table 11-5 shows the interaction of the
CD and NW flags.
The effect of setting the CD flag is somewhat different for processor families
starting with P6 family than the Pentium processor (see Table 11-5). To insure
memory coherency after the CD flag is set, the caches should be explicitly
flushed (see Section 11.5.3, “Preventing Caching”). Setting the CD flag for the
P6 and more recent processor families modify cache line fill and update
behaviour. Also, setting the CD flag on these processors do not force strict
ordering of memory accesses unless the MTRRs are disabled and/or all memory
is referenced as uncached (see Section 8.2.5, “Strengthening or Weakening the
Memory-Ordering Model”).