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9-14 Vol. 3
PROCESSOR MANAGEMENT AND INITIALIZATION
9.8.4 Initializing Multitasking
If the multitasking mechanism is not going to be used and changes between privilege
levels are not allowed, it is not necessary load a TSS into memory or to initialize the
task register.
If the multitasking mechanism is going to be used and/or changes between privilege
levels are allowed, software initialization code must load at least one TSS and an
accompanying TSS descriptor. (A TSS is required to change privilege levels because
pointers to the privileged-level 0, 1, and 2 stack segments and the stack pointers for
these stacks are obtained from the TSS.) TSS descriptors must not be marked as
busy when they are created; they should be marked busy by the processor only as a
side-effect of performing a task switch. As with descriptors for LDTs, TSS descriptors
reside in the GDT.
After the processor has switched to protected mode, the LTR instruction can be used
to load a segment selector for a TSS descriptor into the task register. This instruction
marks the TSS descriptor as busy, but does not perform a task switch. The processor
can, however, use the TSS to locate pointers to privilege-level 0, 1, and 2 stacks. The
segment selector for the TSS must be loaded before software performs its first task
switch in protected mode, because a task switch copies the current task state into
the TSS.
After the LTR instruction has been executed, further operations on the task register
are performed by task switching. As with other segments and LDTs, TSSs and TSS
descriptors can be either pre-allocated or allocated as needed.
9.8.5 Initializing IA-32e Mode
On Intel 64 processors, the IA32_EFER MSR is cleared on system reset. The oper-
ating system must be in protected mode with paging enabled before attempting to
initialize IA-32e mode. IA-32e mode operation also requires physical-address exten-
sions with four levels of enhanced paging structures (see Section 4.5, “IA-32e
Paging”).
Operating systems should follow this sequence to initialize IA-32e mode:
1. Starting from protected mode, disable paging by setting CR0.PG = 0. Use the
MOV CR0 instruction to disable paging (the instruction must be located in an
identity-mapped page).
2. Enable physical-address extensions (PAE) by setting CR4.PAE = 1. Failure to
enable PAE will result in a #GP fault when an attempt is made to initialize IA-32e
mode.
3. Load CR3 with the physical base address of the Level 4 page map table (PML4).
4. Enable IA-32e mode by setting IA32_EFER.LME = 1.
5. Enable paging by setting CR0.PG = 1. This causes the processor to set the
IA32_EFER.LMA bit to 1. The MOV CR0 instruction that enables paging and the