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Vol. 3 10-35
ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)
10.6.3.1 x2APIC Differences in Error Handling
RDMSR and WRMSR operations to reserved addresses in the x2APIC mode will raise
a GP fault. Additionally reserved bit violations cause GP faults as detailed in
Section
10.5.1.3. Beyond illegal register access and reserved bit violations, other APIC errors
are logged in Error Status Register. Writes of a non-zero value to the Error Status
Register in x2APIC mode will raise a GP fault.
Write to the ICR (in xAPIC and x2APIC modes) or to SELF IPI register (x2APIC mode
only) with an illegal vector (vector <= 0FH) will set the "Send Illegal Vector" bit.
On receiving an IPI with an illegal vector (vector <= 0FH), the "Receive Illegal
Vector" bit will be set. On receiving an interrupt with illegal vector in the range 0H -
0FH, the interrupt will not be delivered to the processor nor will an IRR bit be set in
that range. Only the ESR "Receive Illegal Vector" bit will be set.
Table 10-5. ESR Flags
FLAG Function
Send Checksum Error (P6 family and Pentium processors only) Set when the local APIC
detects a checksum error for a message that it sent on the APIC bus.
Receive Checksum Error (P6 family and Pentium processors only) Set when the local APIC
detects a checksum error for a message that it received on the APIC
bus.
Send Accept Error (P6 family and Pentium processors only) Set when the local APIC
detects that a message it sent was not accepted by any APIC on the
APIC bus.
Receive Accept Error (P6 family and Pentium processors only) Set when the local APIC
detects that the message it received was not accepted by any APIC
on the APIC bus, including itself.
Send Illegal Vector Set when the local APIC detects an illegal vector in the message that
it is sending.
Receive Illegal Vector Set when the local APIC detects an illegal vector in the message it
received, including an illegal vector code in the local vector table
interrupts or in a self-interrupt.
Illegal Reg. Address (Intel Core, Intel Atom, Pentium 4, Intel Xeon, and P6 family
processors only) Set when the processor is trying to access a
register in the processor's local APIC register address space that is
reserved (see
Table 10-1). Addresses in one of the 0x10 byte
regions marked reserved are illegal register addresses.
The Local APIC Register Map is the address range of the APIC
register base address (specified in the IA32_APIC_BASE MSR) plus
4
KBytes.