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CONTENTS
xxxviii Vol. 3A
PAGE
TABLES
Table 2-1. Action Taken By x87 FPU Instructions for Different
Combinations of EM, MP, and TS2-21
Table 2-2. Summary of System Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-27
Table 3-1. Code- and Data-Segment Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17
Table 3-2. System-Segment and Gate-Descriptor Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19
Table 4-1. Properties of Different Paging Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3
Table 4-3. Use of CR3 with 32-Bit Paging. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9
Table 4-2. Paging Structures in the Different Paging Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9
Table 4-4. Format of a 32-Bit Page-Directory Entry that Maps a 4-MByte Page. . . . . . . . . . . 4-12
Table 4-5. Format of a 32-Bit Page-Directory Entry that References a Page Table. . . . . . . . 4-13
Table 4-6. Format of a 32-Bit Page-Table Entry that Maps a 4-KByte Page. . . . . . . . . . . . . . . 4-14
Table 4-7. Use of CR3 with PAE Paging. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-16
Table 4-8. Format of an PAE Page-Directory-Pointer-Table Entry (PDPTE). . . . . . . . . . . . . . . . 4-17
Table 4-9. Format of a PAE Page-Directory Entry that Maps a 2-MByte Page . . . . . . . . . . . . . 4-20
Table 4-10. Format of a PAE Page-Directory Entry that References a Page Table . . . . . . . . . . 4-21
Table 4-11. Format of a PAE Page-Table Entry that Maps a 4-KByte Page . . . . . . . . . . . . . . . . . 4-22
Table 4-12. Use of CR3 with IA-32e Paging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-24
Table 4-13. Format of an IA-32e PML4 Entry (PML4E) that References a Page-Directory-Pointer
Table4-27
Table 4-15. Format of an IA-32e Page-Directory Entry that Maps a 2-MByte Page . . . . . . . . . 4-28
Table 4-14. Format of an IA-32e Page-Directory-Pointer-Table Entry (PDPTE) that References a
Page Directory4-28
Table 4-16. Format of an IA-32e Page-Directory Entry that References a Page Table . . . . . . 4-30
Table 4-17. Format of an IA-32e Page-Table Entry that Maps a 4-KByte Page . . . . . . . . . . . . . 4-31
Table 5-1. Privilege Check Rules for Call Gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-23
Table 5-2. 64-Bit-Mode Stack Layout After CALLF with CPL Change. . . . . . . . . . . . . . . . . . . . . . 5-28
Table 5-3. Combined Page-Directory and Page-Table Protection . . . . . . . . . . . . . . . . . . . . . . . . . 5-42
Table 5-4. Extended Feature Enable MSR (IA32_EFER) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-43
Table 5-5. IA-32e Mode Page Level Protection Matrix
with Execute-Disable Bit Capability5-44
Table 5-6. Legacy PAE-Enabled 4-KByte Page Level Protection Matrix
with Execute-Disable Bit Capability5-45
Table 5-7. Legacy PAE-Enabled 2-MByte Page Level Protection
with Execute-Disable Bit Capability5-45
Table 5-8. IA-32e Mode Page Level Protection Matrix with Execute-Disable Bit Capability
Enabled5-46
Table 5-9. Reserved Bit Checking WIth Execute-Disable Bit Capability Not Enabled. . . . . . . . 5-47
Table 6-1. Protected-Mode Exceptions and Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3
Table 6-2. Priority Among Simultaneous Exceptions and Interrupts . . . . . . . . . . . . . . . . . . . . . . 6-11
Table 6-3. Debug Exception Conditions and Corresponding Exception Classes. . . . . . . . . . . . . 6-29
Table 6-4. Interrupt and Exception Classes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-38
Table 6-5. Conditions for Generating a Double Fault. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-39
Table 6-6. Invalid TSS Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-42
Table 6-7. Alignment Requirements by Data Type. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-60
Table 6-8. SIMD Floating-Point Exceptions Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-65
Table 7-1. Exception Conditions Checked During a Task Switch . . . . . . . . . . . . . . . . . . . . . . . . . . 7-15
Table 7-2. Effect of a Task Switch on Busy Flag, NT Flag,
Previous Task Link Field, and TS Flag7-17
Table 8-1. Initial APIC IDs for the Logical Processors in a System that has Four Intel Xeon MP
Processors Supporting Intel Hyper-Threading Technology
18-52