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Vol. 3 19-43
ARCHITECTURE COMPATIBILITY
sors. The following sections describe these model-specific extensions. The CPUID
instruction indicates the availability of some of the model-specific features.
19.37.1 Model-Specific Registers
The Pentium processor introduced a set of model-specific registers (MSRs) for use in
controlling hardware functions and performance monitoring. To access these MSRs,
two new instructions were added to the IA-32 architecture: read MSR (RDMSR) and
write MSR (WRMSR). The MSRs in the Pentium processor are not guaranteed to be
duplicated or provided in the next generation IA-32 processors.
The P6 family processors greatly increased the number of MSRs available to soft-
ware. See Appendix B, “Model-Specific Registers (MSRs),” for a complete list of the
available MSRs. The new registers control the debug extensions, the performance
counters, the machine-check exception capability, the machine-check architecture,
and the MTRRs. These registers are accessible using the RDMSR and WRMSR instruc
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tions. Specific information on some of these new MSRs is provided in the following
sections. As with the Pentium processor MSR, the P6 family processor MSRs are not
guaranteed to be duplicated or provided in the next generation IA-32 processors.
19.37.2 RDMSR and WRMSR Instructions
The RDMSR (read model-specific register) and WRMSR (write model-specific
register) instructions recognize a much larger number of model-specific registers in
the P6 family processors. (See “RDMSR—Read from Model Specific Register” and
“WRMSR—Write to Model Specific Register” in the
Intel® 64 and IA-32 Architectures
Software Developer’s Manual, Volumes 2A & 2B for more information.)
19.37.3 Memory Type Range Registers
Memory type range registers (MTRRs) are a new feature introduced into the IA-32 in
the Pentium Pro processor. MTRRs allow the processor to optimize memory opera
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tions for different types of memory, such as RAM, ROM, frame buffer memory, and
memory-mapped I/O.
MTRRs are MSRs that contain an internal map of how physical address ranges are
mapped to various types of memory. The processor uses this internal memory map
to determine the cacheability of various physical memory locations and the optimal
method of accessing memory locations. For example, if a memory location is speci
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fied in an MTRR as write-through memory, the processor handles accesses to this
location as follows. It reads data from that location in lines and caches the read data
or maps all writes to that location to the bus and updates the cache to maintain cache
coherency. In mapping the physical address space with MTRRs, the processor recog
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nizes five types of memory: uncacheable (UC), uncacheable, speculatable, write-
combining (WC), write-through (WT), write-protected (WP), and writeback (WB).