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Vol. 3 15-13
MACHINE-CHECK ARCHITECTURE
• Recoverable Address LSB (bits 5:0): The lowest valid recoverable address bit.
Indicates the position of the least significant bit (LSB) of the recoverable error
address. For example, if the processor logs bits [43:9] of the address, the LSB
sub-field in IA32_MCi_MISC is 01001b (9 decimal). For this example, bits [8:0]
of the recoverable error address in IA32_MCi_ADDR should be ignored.
• Address Mode (bits 8:6): Address mode for the address logged in
IA32_MCi_ADDR. The supported address modes are given in Table 15-3.
• Model Specific Information (bits 63:9): Not architecturally defined.
15.3.2.5 IA32_MCi_CTL2 MSRs
The IA32_MCi_CTL2 MSR provides the programming interface to use
corrected MC error signaling capability that is indicated by
IA32_MCG_CAP[10] = 1. Software must check for the presence of
IA32_MCi_CTL2 on a per-bank basis.
Figure 15-7. UCR Support in IA32_MCi_MISC Register
Table 15-3. Address Mode in IA32_MCi_MISC[8:6]
IA32_MCi_MISC[8:6] Encoding Definition
000 Segment Offset
001 Linear Address
010 Physical Address
011 Memory Address
100 to 110 Reserved
111 Generic
Address Mode
63
0
Model Specific Information
6 5
Recoverable Address LSB
89