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16-14 Vol. 3
DEBUGGING, PROFILING BRANCHES AND TIME-STAMP COUNTER
16.4 LAST BRANCH, INTERRUPT, AND EXCEPTION
RECORDING OVERVIEW
P6 family processors introduced the ability to set breakpoints on taken branches,
interrupts, and exceptions, and to single-step from one branch to the next. This
capability has been modified and extended in the Pentium 4, Intel Xeon, Pentium M,
Intel
®
Core™ Solo, Intel
®
Core™ Duo, Intel
®
Core™2 Duo, Intel
®
Core™ i7 and
Intel
®
Atom™ processors to allow logging of branch trace messages in a branch trace
store (BTS) buffer in memory.
See the following sections for processor specific implementation of last branch, inter-
rupt and exception recording:
— Section 16.5, “Last Branch, Interrupt, and Exception Recording (Intel
®
Core
™
2 Duo and Intel
®
Atom
™
Processor Family)”
— Section 16.6, “Last Branch, Interrupt, and Exception Recording (Intel
®
Core
™
i7 Processor Family)”
— Section 16.7, “Last Branch, Interrupt, and Exception Recording (Processors
based on Intel NetBurst
®
Microarchitecture)”
— Section 16.8, “Last Branch, Interrupt, and Exception Recording (Intel
®
Core
™
Solo and Intel
®
Core
™
Duo Processors)”
— Section 16.9, “Last Branch, Interrupt, and Exception Recording (Pentium M
Processors)”
— Section 16.10, “Last Branch, Interrupt, and Exception Recording (P6 Family
Processors)”
The following subsections of Section 16.4 describe common features of profiling
branches. These features are generally enabled using the IA32_DEBUGCTL MSR
(older processor may have implemented a subset or model-specific features, see
definitions of MSR_DEBUGCTLA, MSR_DEBUGCTLB, MSR_DEBUGCTL).
16.4.1 IA32_DEBUGCTL MSR
The IA32_DEBUGCTL MSR provides bit field controls to enable debug trace inter-
rupts, debug trace stores, trace messages enable, single stepping on branches, last
branch record recording, and to control freezing of LBR stack or performance
counters on a PMI request. IA32_DEBUGCTL MSR is located at register address
01D9H.
See Figure 16-3 for the MSR layout and the bullets below for a description of the
flags:
• LBR (last branch/interrupt/exception) flag (bit 0) — When set, the
processor records a running trace of the most recent branches, interrupts, and/or
exceptions taken by the processor (prior to a debug exception being generated)